Senior Physical Design Engineer – Timing & 7nm+

eTeam; Palo Alto (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

eTeam in Palo Alto seeks an experienced engineer to lead end-to-end physical design flows, including floorplanning, power planning, placement, CTS, routing and post-route optimization. You will ensure timing closure across modes and corners while resolving DRC/LVS/ERC issues and signoff requirements.

Collaborating with RTL and micro-architecture teams, DFT and test engineers, as well as foundry and CAD teams, you will work on advanced nodes (7nm, 5nm, 3nm or below) and help drive design

Responsibilities

• Perform end-to-end physical design flow: Floorplanning, Power planning (PG grid, IR), Placement & optimization, CTS (Clock Tree Synthesis), Routing, Post-route optimization
• Achieve timing closure across all modes and corners
• Resolve DRC, LVS, ERC and signoff violations
• Multi-Vt, Multi-voltage (UPF)
• Perform physical verification and signoff: STA (Primetime), SI / Crosstalk, IR drop & EM analysis
• Work on advanced nodes (7nm, 5nm, 3nm or below)
• Collaborate with: RTL & Micro-architecture teams, DFT & Test engineers, Foundry and CAD teams
• Debug complex timing, congestion, power, and variability issues
• Drive methodology improvements and automation (scripts/flows)

Job description

eTeam in Palo Alto seeks an experienced engineer to lead end-to-end physical design flows, including floorplanning, power planning, placement, CTS, routing and post-route optimization. You will ensure timing closure across modes and corners while resolving DRC/LVS/ERC issues and signoff requirements.

Collaborating with RTL and micro-architecture teams, DFT and test engineers, as well as foundry and CAD teams, you will work on advanced nodes (7nm, 5nm, 3nm or below) and help drive design