Senior Physical Design Engineer: Tapeout Ready

Analog Devices; New Jersey; On-site; USD 116,960 - 160,820; Full time

Benefits offered by this job

Medical insurance

Vision insurance

Dental insurance

401k

Paid time off

Discretionary bonus

Job summary

Analog Devices is seeking a Senior Physical Design Engineer to drive the back-end implementation of complex digital/mixed-signal ICs. You will own floorplanning, placement, clock-tree synthesis, routing, and timing closure, coordinating with RTL, verification, DFT, STA, and package teams to ensure successful tapeout.

The role emphasizes strong debugging, constraint development, and flow improvements, with opportunities to mentor junior engineers and contribute to methodology enhancements.

Qualifications

• 5+ years of experience in physical design for ASIC/SoC development.
• Strong background in floorplanning, P&R, CTS, timing closure, and signoff.
• Experience with timing, SI, power optimization, and physical trade-offs.
• Excellent collaboration with RTL, verification, DFT, STA, and package teams.

Responsibilities

• Own physical design implementation for complex digital blocks and subsystems.
• Drive timing closure, congestion analysis, power optimization, and area improvement.
• Perform DRC/LVS/ERC and reliability checks with cross-functional teams.
• Develop constraints and flows to improve quality and efficiency.
• Support tapeout planning and handle interface timing and readiness.

Skills

Physical design

Floorplanning

Place-and-route

Timing closure

Clock tree synthesis

Scripting (TCL, Python)

DRC/LVS/ERC debugging

Collaboration across RTL/STA/DFT

Education

Bachelor’s degree in Electrical/Computer Engineering or related field

Master’s degree in Electrical/Computer Engineering or related field

Tools

Cadence flows

Job description

Analog Devices is seeking a Senior Physical Design Engineer to drive the back-end implementation of complex digital/mixed-signal ICs. You will own floorplanning, placement, clock-tree synthesis, routing, and timing closure, coordinating with RTL, verification, DFT, STA, and package teams to ensure successful tapeout.

The role emphasizes strong debugging, constraint development, and flow improvements, with opportunities to mentor junior engineers and contribute to methodology enhancements.