Physical Design Engineer (PnR / PPA / Timing Closure)

Wipro Technologies; Austin (TX); On-site; USD 100,000 - 180,000; Full time

Benefits offered by this job

Full range of medical and dental\nbene

Disability insurance

Paid time off

Job summary

Wipro Limited in Austin, Texas is seeking a Physical Design Engineer with strong PnR, PPA optimization, and timing convergence to drive block-level design from netlist to GDSII. You will perform floorplanning, CTS, routing, and timing closure across advanced nodes, collaborating with RTL/STA/Signoff teams to tape out complex silicon.

The role requires 8–10 years in VLSI physical design, expertise with Fusion Compiler/ICC2 and PrimeTime, and hands-on PPA and EMIR analysis.

Qualifications

• 8–10 years of experience in VLSI Physical Place and Route (PnR) and related signoff
• Experience with 7nm/5nm/3nm nodes preferred
• Strong debugging and problem-solving skills in physical design and PPA
• Proficiency with industry-standard EDA tools listed in the job description

Responsibilities

• Drive block-level physical design implementation from netlist to GDSII
• Perform floorplanning, power planning, placement, CTS, routing, and physical verification
• Optimize designs for Power, Performance, and Area (PPA) targets
• Achieve timing closure across corners and modes
• Analyze and resolve timing violations and EMIR-related issues
• Develop and maintain timing constraints (SDC) and STA signoff methodologies
• Collaborate with RTL, DFT, STA, and Signoff teams for tapeout
• Debug physical design issues and drive design convergence within project schedules

Skills

Physical Design

PnR

Floorplanning

Placement

CTS

Routing

Timing Closure

STA

EMIR

PPA optimization

SDC constraints

Education

Bachelor's degree in Electrical/Electronics Engineering

Tools

Fusion Compiler

ICC2

PrimeTime

Innovus

RedHawk

Voltus

Job description

Physical Design Engineer (PnR / PPA / Timing Closure) Job Description Job Title: Physical Design Engineer (PnR / PPA / Timing Closure) City: Austin, Mountain View State/Province: California, Texas Posting Start Date: 9/25/26 Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients’ most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com.

Job Description

We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes.

Key Responsibilities

• Drive block-level physical design implementation from netlist to GDSII.
• Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification.
• Optimize designs for Power, Performance, and Area (PPA) targets.
• Achieve timing closure across multiple corners and modes.
• Analyze and resolve setup, hold, transition, capacitance, and noise violations.
• Develop and maintain timing constraints (SDC) and STA signoff methodologies.
• Perform EMIR (Electromigration & IR Drop) analysis and closure.
• Collaborate with RTL, DFT, STA, and Signoff teams to ensure successful tapeout.
• Debug physical design issues and drive design convergence within project schedules.

Required Skills

• Strong experience in Physical Design and PnR flow.
• Hands‑on expertise in:
  • Floorplanning
  • Placement & Optimization
  • Clock Tree Synthesis (CTS)
  • Routing
  • Timing Closure
  • Static Timing Analysis (STA)
  • Timing Constraints (SDC)
  • EMIR Analysis
  • PPA Optimization
• Experience with industry-standard EDA tools such as:
  • Synopsys Fusion Compiler / ICC2
  • PrimeTime
  • Cadence Innovus (optional)
  • RedHawk / Voltus (EMIR)
• Good understanding of low-power design techniques and signoff methodologies.

Preferred Qualifications

• Bachelor's or Master's degree in Electrical/Electronics Engineering.
• Experience in advanced nodes (7nm/5nm/3nm preferred).
• Strong debugging and problem-solving skills.
• Experience working with cross-functional silicon teams.

Mandatory Skills: VLSI Physical Place and Route.Experience: 8-10 Years.

The expected compensation for this role ranges from $100,000 to $180,000 .

Final compensation will depend on various factors, including your geographical location, minimum wage obligations, skills, and relevant experience.

• full range of medical and dental benefits options
• disability insurance
• paid time off (inclusive of sick leave)
• other paid and unpaid leave options

Applicants are advised that employment in some roles may be conditioned on successful completion of a post-offer drug screening, subject to applicable state law.

Wipro provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state, or local laws. Applications from veterans and people with disabilities are explicitly welcome.

We are an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, caste, creed, religion, gender, marital status, age, ethnic and national origin, gender identity, gender expression, sexual orientation, political orientation, disability status, protected veteran status, or any other characteristic protected by law.

Wipro is committed to creating an accessible, supportive, and inclusive workplace. Reasonable accommodation will be provided to all applicants including persons with disabilities, throughout the recruitment and selection process. Accommodations must be communicated in advance of the application, where possible, and will be reviewed on an individual basis. Wipro provides equal opportunities to all and values diversity.

Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention.

Information at a Glance

Get Job Alerts

Receive notifications when we have open roles and get other relevant career news

Join Us

Explore open rolesthat match your interests and skills

If you encounter any suspicious mail, advertisements, or persons who offer jobs at Wipro, please email us at [e-mail] . Do not email your resume to this ID as it is not monitored for resumes and career applications.

Any complaints or concerns regarding unethical/unfair hiring practices should be directed to our Ombuds Group at [e-mail] .

© 2026 Wipro Limited