Senior Physical Design Engineer for AI Accelerator

Careerwebsite; Mountain View (CA); Hybrid; USD 230,000 - 320,000; Full time

Benefits offered by this job

Equity grant

Medical / Dental / Vision

401(k)

Standard PTO

Job summary

DensityAI is seeking an experienced physical design engineer to own floorplan-to-signoff for AI accelerator silicon in California. You will collaborate with chip-Design and software teams to bring blocks from RTL to tapeout in a scalable flow.

You will use and extend AI-assisted PD tool flows, working closely with architects and foundries, applying advanced signoff knowledge to meet aggressive timing and power goals.

Qualifications

• 8+ years of experience in very high performance designs at 7nm or better.
• Hands-on with PD tools and signoff.
• Ability to work with architects, RTL designers, EDA vendors, and foundries.

Responsibilities

• Own floorplan-to-signoff physical design for one or more blocks of AI accelerator silicon.
• Develop and use AI-assisted tool flows to accelerate design and signoff timelines.

Skills

Floorplan-to-signoff PD

High-performance PD flows

Collaboration with architects/RTL

Tools

Cadence Innovus

Synopsys Fusion Compiler

PrimeTime/Tempus

Job description

DensityAI is seeking an experienced physical design engineer to own floorplan-to-signoff for AI accelerator silicon in California. You will collaborate with chip-Design and software teams to bring blocks from RTL to tapeout in a scalable flow.

You will use and extend AI-assisted PD tool flows, working closely with architects and foundries, applying advanced signoff knowledge to meet aggressive timing and power goals.