Physical Design Engineer

Acceler8 Talent; Mountain View (CA); Hybrid; USD 260,000 - 340,000; Full time

Job summary

Acceler8 Talent in Mountain View, CA seeks a Senior Physical Design Engineer to take ownership of physical design for one or more blocks of a new AI accelerator, from initial floorplanning through final sign-off. You will lead synthesis, floorplanning, placement, routing, CTS, and sign-off, and drive timing, power, area, and physical-verification requirements.

Develop AI-assisted flows to accelerate timelines while collaborating with architects, RTL designers, EDA vendors, foundries, and

Qualifications

• 8+ years of hands-on physical-design experience.
• Experience with high-performance designs at 7nm or below.
• Full-flow ownership from synthesis to sign-off.

Responsibilities

• Own synthesis, floorplanning, placement, routing, CTS, and sign-off.
• Close timing, power, area, congestion, and physical-verification requirements.
• Develop AI-assisted flows to accelerate physical-design and sign-off timelines.
• Work with architects and RTL designers to resolve implementation trade-offs.
• Collaborate with EDA vendors, foundries, packaging, and verification teams.
• Deliver complex blocks through tape-out and first silicon.

Skills

Physical design

Timing sign-off

EDA tools

Tape-out experience

Collaboration

Tools

Cadence Innovus

Synopsys Fusion Compiler

PrimeTime/Tempus

Job description

Physical Design Engineer

On-site | Mountain View, CA

$250 + base + equity

I’m working with an AI compute startup rebuilding the hardware and software stack around extreme compute density.

The team is developing a tightly integrated platform spanning advanced silicon, packaging, firmware, compilers, kernels, and infrastructure. This is broader than a conventional accelerator project, with physical-design decisions directly affecting the architecture and performance of the complete system.

This role will own physical design for one or more blocks of a new AI accelerator, from initial floorplanning through final sign-off.

You’ll work on problems such as:

• Owning synthesis, floorplanning, placement, routing, CTS, and sign-off
• Closing timing, power, area, congestion, and physical-verification requirements
• Developing AI-assisted flows to accelerate physical-design and sign-off timelines
• Working with architects and RTL designers to resolve implementation trade-offs
• Collaborating with EDA vendors, foundries, packaging, and verification teams
• Delivering complex blocks through tape-out and first silicon.

Looking for engineers who have:

• 8+ years of hands-on physical-design experience
• Experience with high-performance designs at 7nm or below
• Full-flow ownership from synthesis and floorplanning through sign-off
• Strong experience with Cadence Innovus, Synopsys Fusion Compiler, or equivalent
• Hands-on timing sign-off experience using PrimeTime, Tempus, or equivalent
• Experience working closely with architecture, RTL, foundry, and EDA teams
• A track record of taking complex silicon through tape-out.

Nice to have:

• CoWoS, chiplet, 2.5D, or 3D packaging experience
• Thermal, IR-drop, electromigration, or signal-integrity sign-off
• DFT-aware physical design
• Experience with AI accelerators, CPUs, GPUs, or other high-performance compute silicon
• Experience building or improving physical-design automation.

This is an opportunity to own foundational implementation decisions for a new AI computing platform alongside engineers with experience across advanced CPUs, custom AI silicon, and wafer-scale systems.

Worth a confidential chat?