Physical Design Engineer

DensityAI; Mountain View (CA); On-site; USD 230,000 - 400,000; Full time

Benefits offered by this job

Equity grant

Medical, dental, and vision insurance

401(k)

Standard PTO

Job summary

DensityAI in Mountain View, California is seeking a Senior Physical Design Engineer to lead the physical design for blocks of AI accelerator silicon. The ideal candidate will have over 8 years of experience with high-performance designs at advanced nodes and will be proficient in industry-standard PD tools.

Our compensation package includes a competitive salary range of $230,000 - $400,000, equity grants, and comprehensive benefits. We also offer visa sponsorship for qualified candidates.

Qualifications

• 8+ years of experience on very high-performance designs at advanced technology nodes (7 nm or better).
• Hands-on experience with industry-standard PD tools and signoff.
• Exceptional abilities across the full physical design flow.

Responsibilities

• Own floorplan-to-signoff physical design for blocks of AI accelerator silicon.
• Use and develop AI-assisted tool flows to accelerate physical design.

Skills

Physical design flow (synthesis, place & route, CTS, signoff)

Industry-standard PD tools (Cadence Innovus, Synopsys Fusion Compiler)

Collaboration with architects and EDA vendors

Tools

Cadence Innovus

Synopsys Fusion Compiler

PrimeTime

Tempus

Job description

ITAR Notice: This role involves access to ITAR‑controlled information. Applicants must be U.S. persons (U.S. citizens, U.S. permanent residents, asylees, or refugees) per 22 CFR 120.62.

About The Role

Own floorplan‑to‑signoff physical design for one or more blocks of our AI accelerator silicon. Work with chip‑design and software teams driving DensityAI’s AI accelerator program from first silicon through scale‑out.

Responsibilities

• Own floorplan‑to‑signoff physical design for one or more blocks of our AI accelerator silicon.
• Use and develop AI‑assisted tool flows to accelerate physical design and signoff timelines.

Qualifications

• Exceptional abilities across the full physical design flow (synthesis, place & route, CTS, signoff).
• 8+ years of experience on very high performance designs at advanced technology nodes (7 nm or better).
• Hands‑on with industry‑standard PD tools (Cadence Innovus, Synopsys Fusion Compiler, or equivalent) and signoff (PrimeTime, Tempus, or equivalent).
• Demonstrated ability to work closely with architects, RTL designers, EDA vendors, and foundries to design and sign off complex chips.
• (Optional) Multi‑die packaging (CoWoS, 2.5D / 3D), thermal / IR / EM signoff, signal integrity, or DFT‑aware physical design.

Compensation

Final offers depend on level, location, and skills relevant to the role. Additional compensation: equity grant per company guidelines; medical / dental / vision; 401(k); standard PTO.

Full compensation packages are based on candidate experience and relevant certifications.

California pay range: $230,000 - $400,000 USD.

Visa Sponsorship

DensityAI sponsors qualified candidates for H‑1B, O‑1, TN, E‑3, and other employment‑based visas, and we welcome applicants on F‑1 OPT and STEM‑OPT. Work authorization is required at start; we provide immigration support to secure or transfer status.

Export Controls

Aspects of this role may involve access to information subject to U.S. export controls (EAR/ITAR). We may discuss licensing or scope adjustments during the interview.

Equal Opportunity

DensityAI is an Equal Opportunity Employer. We do not discriminate on the basis of race, color, religious creed, national origin, ancestry, physical or mental disability, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, age (40+), sexual orientation, military or veteran status, pregnancy, or any other status protected by law. We comply with the California CROWN Act and provide reasonable accommodations on request.