Physical Design Engineer

Technical-Link N. America; San Jose (CA); On-site; USD 120,000 - 150,000; Full time

Job summary

Technical-Link N. America is seeking a seasoned Physical Design professional to drive power-grid and clock constraint strategies across chip layers. You will debug LVS/DRC issues at both chip and block levels and contribute to the tape-out readiness with close collaboration with foundries.

The ideal candidate has deep experience with physical design verification, CDC/STA methodologies, and mixed-signal environments, using Caliber and Redhawk for power analysis and assurance.

Qualifications

• Deep knowledge of Physical Design standards and flows.
• Experience with Power-grid and high-speed clock constraints.
• Ability to debug LVS/DRC issues at chip and block level.
• Familiar with CDC and static timing analysis methodologies.
• Experience with mixed-signal environments.

Responsibilities

• Develop and implement power-grid and high-speed clock constraints.
• Apply physical design verification methodologies to ensure LVS/DRC compliance.
• Debug LVS/DRC issues at chip and block level.
• Coordinate with foundries during tape-out and supply chain activities.
• Utilize Caliber/Redhawk tools for power analysis and verification.

Skills

Physical Design

Clock constraints

Power constraints

LVS/DRC debugging

Mixed-signal experience

Tools

Caliber

Redhawk

Job description

• Good understanding of Cadence tools (Innovous, Quantus, Voltus).
• Deep knowledge about industry standards in Physical Design, Physical aware synthesis, Floorplanning, CTS and place and route.
• Experience in developing and implementing Power-grid and high-speed clock constraints and specifications.
• Good understanding of physical design verification methodology to debug LVS/DRC issues at the chip and block level.
• Experience with CDC, static timing analysis methodologies and relevant tools.
• Understanding and experience of mixed signal environments is a must.
• Candidates must be familiar with Caliber & Redhawk (power analysis) tools.
• Good understanding of design tape-out to foundries and solid understanding of supply chain for IC Product development.