Senior Photonics Layout Engineer — High-Speed PICs

NVIDIA Corporation; Santa Clara (CA); Hybrid; USD 148,000 - 276,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA Corporation in Santa Clara is seeking a Senior Photonics Layout Design Engineer to own the physical design and verification of cutting‑edge photonic integrated circuits (PICs). You will guide designs from proof‑of‑concept to high‑volume manufacturing, collaborating with photonics, CMOS, packaging, and systems engineers to enable next‑gen Silicon Photonics and SERDES products.

The role emphasizes complex tape‑out ownership, automated layout workflows, and AI‑assisted design methods.

Qualifications

• Requires BS/MS/PhD in EE, Physics, or related field or equivalent experience.
• 12+ years of hands-on full-chip layout design in semiconductor, analog, or silicon photonics industries.
• Deep understanding of analog circuit layout, Silicon Photonic constraints, and device physics in sub‑micron CMOS and SiPh.

Responsibilities

• Lead full-loop manual and automated layout designs for waveguides, modulators, photodetectors, and mixed-signal I/Os.
• Execute post-layout verification (DRC, LVS, fill, density) and mitigate layout‑dependent issues before tape-out.
• Own layout of complex test structures and DOE‑driven validation to optimize process windows.
• Develop AI-assisted design methods and layout automation scripts to improve productivity and reduce cycle times.

Skills

Python

SKILL

Perl

TCL

C++

Layout automation

Workflow optimization

Education

BS/MS/PhD in Electrical Engineering or Physics or related

Tools

Cadence Virtuoso

Calibre

Hercules

ICV

Dracula

Primeyield

Job description

NVIDIA Corporation in Santa Clara is seeking a Senior Photonics Layout Design Engineer to own the physical design and verification of cutting‑edge photonic integrated circuits (PICs). You will guide designs from proof‑of‑concept to high‑volume manufacturing, collaborating with photonics, CMOS, packaging, and systems engineers to enable next‑gen Silicon Photonics and SERDES products.

The role emphasizes complex tape‑out ownership, automated layout workflows, and AI‑assisted design methods.