Photonic Engineer

Acceler8 Talent; Berkeley (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Acceler8 Talent is seeking a senior Photonic IC Layout & Design Flow Engineer to own the PIC layout, verification, signoff and tape-out, connecting photonic designs with electronic IC development, packaging and silicon validation.

You will establish and drive a Cadence Photonics workflow for GlobalFoundries’ 45 nm process, coordinate component designers, and ensure a complete, manufacturable PIC delivery from layout through tape-out.

Qualifications

• At least one complete industry PIC tape-out with chip-level layout, verification and signoff.
• Strong practical experience with Cadence Photonics, Virtuoso or similar PIC flow.
• Experience building or improving design flows, not just using an existing workflow.
• Solid understanding of silicon-photonics device physics with design/simulation.
• Collaborating with electronic IC, packaging and characterization engineers.

Responsibilities

• Own chip-level layout, component integration, DRC/LVS, signoff and tape-out readiness.
• Build and improve PDK, layout and verification workflows for repeatable chip delivery.
• Make photonic design flow compatible with electronic IC work underway.
• Resolve layout and interface requirements across PICs, EICs and packaging.
• Work with measurement teams to connect silicon results with design improvements.
• Provide technical direction while remaining hands-on with implementation and verification.

Skills

Cadence Photonics

Virtuoso

PIC layout

DRC/LVS

Team leadership

Tools

PDK development

CAD tooling automation

Job description

Photonic IC Layout & Design Flow Engineer

Have you personally taken a complete photonic IC through layout, verification, signoff and tape‑out?

We’re working with a photonic computing company developing an integrated optical‑electronic platform for AI workloads. They’re hiring a senior, hands‑on engineer to own the PIC layout and design flow, connecting photonic designs with electronic IC development, packaging and silicon validation.

The core requirement is personal ownership of a complete industry PIC tape‑out. You should be able to explain what you implemented, which verification and signoff decisions you owned, and how you took the design through foundry submission and silicon delivery.

The role

You’ll establish and own a Cadence‑based photonics workflow for GlobalFoundries’ 45 nm process, coordinating component designers and driving a complete, manufacturable PIC layout.

Your responsibilities will include:

• Owning chip‑level layout, component integration, PDK checks, DRC/LVS, signoff and tape‑out readiness.
• Building and improving the PDK, layout and verification workflows needed for repeatable chip delivery.
• Making the photonic design flow compatible with the electronic IC work already underway.
• Resolving layout and interface requirements across PICs, EICs and packaging.
• Working with measurement and characterization teams to connect silicon results with design improvements.
• Providing technical direction to other photonic engineers while remaining hands‑on with implementation and verification.

The first six months will focus on completing the Cadence Photonics workflow for the GlobalFoundries 45 nm process and integrating it with the EIC design flow.

Your experience

• At least one complete industry PIC tape‑out, with direct responsibility for chip‑level layout, verification and signoff.
• Strong practical experience with Cadence Photonics, Virtuoso or a closely related commercial PIC flow.
• Experience building or improving design flows, rather than simply using an established workflow.
• A strong understanding of silicon‑photonics device physics, supported by meaningful device or circuit design and simulation experience.
• Practical collaboration with electronic IC, packaging and characterization engineers.
• The ability to coordinate specialist designers and remain accountable for complete chip delivery.

This is an opportunity to own a substantial part of a new computing platform, with direct founder access and close collaboration across photonics, electronics, packaging and lab validation.

You’ll help shape the workflows and engineering decisions that take research silicon toward a commercial system.