Senior Photonic Layout Engineer - Tape-Out Lead

Acceler8 Talent; California; On-site; USD 150,000 - 230,000; Full time

Benefits offered by this job

Medical insurance

Vision insurance

Dental insurance

401(k)

Job summary

Acceler8 Talent seeks a Senior Photonic Layout Engineer in Berkeley, CA, to own the photonic layout and tape-out flow, interfacing PIC development with electronic IC work. The role emphasizes Cadence-based workflows for a 45 nm process and close collaboration across PIC, EIC, and packaging teams.

Candidates should have direct PIC design ownership, strong Cadence experience, and a track record of tape-out-ready photonic designs, including foundry PDKs and DRC/LVS alignment.

Qualifications

• Direct PIC design experience with ownership of layout implementation and verification.
• Hands-on Cadence experience connecting photonic and electronic design flows.
• Experience taking commercial photonic designs toward tape-out with own sign-off.
• Ownership of foundry PDKs, DRC/LVS, and design-rule compliance.

Responsibilities

• Own the photonic layout flow from design to tape-out release.
• Establish Cadence Photonics workflow for 45 nm process, aligning with IC flow.
• Implement photonic and electronic layout and routing, resolving cross-domain interfaces.
• Manage netlisting and PDK integration to meet manufacturing requirements.

Skills

PIC design ownership

Cadence proficiency

Photonic-electronic interface

Foundry PDK familiarity

Layout verification & tape-out

Device physics understanding

Cross-domain collaboration

Tools

Cadence

PDK integration

Job description

Acceler8 Talent seeks a Senior Photonic Layout Engineer in Berkeley, CA, to own the photonic layout and tape-out flow, interfacing PIC development with electronic IC work. The role emphasizes Cadence-based workflows for a 45 nm process and close collaboration across PIC, EIC, and packaging teams.

Candidates should have direct PIC design ownership, strong Cadence experience, and a track record of tape-out-ready photonic designs, including foundry PDKs and DRC/LVS alignment.