Photonic Layout Engineer

Acceler8 Talent; California; Presencial; USD 150.000 - 230.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Medical insurance

Vision insurance

Dental insurance

401(k)

Descripción de la vacante

Acceler8 Talent seeks a Senior Photonic Layout Engineer in Berkeley, CA, to own the photonic layout and tape-out flow, interfacing PIC development with electronic IC work. The role emphasizes Cadence-based workflows for a 45 nm process and close collaboration across PIC, EIC, and packaging teams.

Candidates should have direct PIC design ownership, strong Cadence experience, and a track record of tape-out-ready photonic designs, including foundry PDKs and DRC/LVS alignment.

Formación

• Direct PIC design experience with ownership of layout implementation and verification.
• Hands-on Cadence experience connecting photonic and electronic design flows.
• Experience taking commercial photonic designs toward tape-out with own sign-off.
• Ownership of foundry PDKs, DRC/LVS, and design-rule compliance.

Responsabilidades

• Own the photonic layout flow from design to tape-out release.
• Establish Cadence Photonics workflow for 45 nm process, aligning with IC flow.
• Implement photonic and electronic layout and routing, resolving cross-domain interfaces.
• Manage netlisting and PDK integration to meet manufacturing requirements.

Conocimientos

PIC design ownership

Cadence proficiency

Photonic-electronic interface

Foundry PDK familiarity

Layout verification & tape-out

Device physics understanding

Cross-domain collaboration

Herramientas

Cadence

PDK integration

Descripción del empleo

Senior Photonic Layout Engineer

Berkeley, CA

$150k–approximately $230k

*Open to PHD candidates - Senior.

We’re working with an early-stage photonic computing company developing an integrated optical-electronic platform for AI workloads. The approach uses light to address the power, data-movement and compute-density challenges of conventional electronic accelerators.

The work spans photonic compute, electronic ICs, packaging, memory and system architecture, with a focus on turning research silicon into a commercial computing platform.

They’re hiring a Senior Photonic Layout Engineer to own the photonic layout and tape-out flow, connecting PIC development with the electronic IC work already underway.

The role

• Own the photonic layout flow from design implementation and routing through verification, sign-off and tape-out release.


• Establish a Cadence Photonics workflow for GlobalFoundries’ 45 nm process, compatible with the electronic IC design flow.


• Personally implement photonic and electronic layout and routing within Cadence, resolving interfaces between the two domains.


• Own netlisting, DRC/LVS and foundry/PDK integration, ensuring designs meet manufacturing requirements.

Your experience

• Direct PIC design experience, with substantial personal ownership of layout implementation, routing and verification.


• Strong hands‑on Cadence experience, including practical work connecting photonic and electronic design flows.


• Experience taking commercial photonic designs toward tape-out, with clear accountability for your own implementation and sign-off work.


• Practical ownership of foundry PDKs, design rules, netlisting and DRC/LVS.


• A strong understanding of silicon‑photonics device physics, supported by device or circuit design and simulation experience.


• The ability to work across PIC, EIC, packaging and lab validation, understanding how layout decisions affect the integrated system.


• Comfort with hands‑on execution, broad responsibility and establishing a design flow within a small team.

Why join?

You’ll own a foundational part of a photonic computing platform while major design and integration decisions are still open. The work connects photonic devices with electronic ICs, packaging and measured hardware performance.

You’ll work directly with a technically deep founding team and help build the workflow that turns individual designs into a complete, manufacturable system.

This is an opportunity for someone who wants to take responsibility for chip‑level implementation and help move photonic computing from research silicon toward a commercial product.

Featured benefits

Medical insurance, Vision insurance, Dental insurance, 401(k)