Senior PCIe Characterization & SI Engineer

Hikinex; Palo Alto (CA); On-site; USD 96,000 - 165,000; Part time

Job summary

Hikinex in Palo Alto, CA seeks a hands-on PCIe Characterization Engineer to perform post-silicon electrical characterization of high-speed SerDes interfaces in a lab.

You will independently operate lab equipment, execute eye, jitter, BER, and S-parameter measurements, read schematics and PCBs, and build Python automation to accelerate silicon validation across PCIe and related interfaces.

Qualifications

• 5+ years in post-silicon characterization or HSIO validation
• Experience with PCIe SerDes PHY characterization
• Capable of measuring eye diagrams, jitter, BER, and S-parameters
• Proficient with high-speed oscilloscopes, BERTs, and VNAs/TDR
• Able to read schematics and PCB layouts
• Python scripting for test automation
• Willing to work on-site in Palo Alto, CA

Responsibilities

• Perform post-silicon electrical characterization of high-speed SerDes PHYs (PCIe, Ethernet, UFS, LPDDR5)
• Operate lab equipment and troubleshoot signal integrity issues
• Analyze results, document configurations and findings
• Develop Python scripts to automate measurements
• Collaborate with engineering teams on validation activities
• Read schematics and PCB layouts to support testing

Skills

Post-silicon characterization

HSIO validation

PCIe SerDes

Eye diagrams

Oscilloscopes & BERT

Schematic reading

Python scripting

Lab debugging

Probe-point debugging

Tools

Vector Network Analyzers (VNA)

BERT

TDR

VNA/TDR equipment

Job description

Hikinex in Palo Alto, CA seeks a hands-on PCIe Characterization Engineer to perform post-silicon electrical characterization of high-speed SerDes interfaces in a lab.

You will independently operate lab equipment, execute eye, jitter, BER, and S-parameter measurements, read schematics and PCBs, and build Python automation to accelerate silicon validation across PCIe and related interfaces.