PCIE Characterization Engineer

eTeam; Palo Alto (CA); Sur place; USD 150 000 - 210 000; Plein temps

Résumé du poste

eTeam in Palo Alto, California, seeks a skilled hardware validation engineer to own post-silicon characterization of SoC PHYs, with hands-on work on PCIe and Ethernet, plus UFS or LPDDR5 familiarity.

You will work with lab equipment like high-speed oscilloscopes, BERT, VNA/TDR, and protocol/logic analyzers, interpreting eye, jitter, BER, and S-parameter data to close silicon issues; reading schematics and debug at probe points.

Qualifications

• 5 years post-silicon electrical characterization, HSIO validation, or memory electrical validation of SoC PHYs.
• Hands-on ownership of PCIe or Ethernet and some experience with UFS or LPDDR5.
• Lab fluency: high-speed oscilloscopes, BERT, VNA/TDR, protocol and logic analyzers; you have personally taken eyes, jitter, BER, and S-parameter data and used it to close a silicon issue
• Working knowledge of signal integrity, SerDes, silicon PVT sensitivity, and JEDEC / PCI-SIG / MIPI-UFS electrical specs
• Ability to read schematics and layout, debug at the probe point, and separate PHY vs. package vs. board vs. firmware
• Scripting for lab automation and data analysis (Python preferred)
• Clear written and verbal communication; you can present a margin plot and a root-cause story to design and program teams.

Connaissances

Hardware validation

PCIe & Ethernet experience

UFS / LPDDR5 familiarity

Lab instrumentation

Signal integrity concepts

Schematic & layout reading

Python scripting

Communication skills

Outils

Oscilloscope

BERT

VNA/TDR

Protocol analyzers

Logic analyzers

Description du poste

• 5 years post-silicon electrical characterization, HSIO validation, or memory electrical validation of SoC PHYs
• Hands-on ownership of PCIe or Ethernet and some experience with UFS or LPDDR5.
• Lab fluency: high-speed oscilloscopes, BERT, VNA/TDR, protocol and logic analyzers; you have personally taken eyes, jitter, BER, and S-parameter data and used it to close a silicon issue
• Working knowledge of signal integrity, SerDes, silicon PVT sensitivity, and JEDEC / PCI-SIG / MIPI-UFS electrical specs
• Ability to read schematics and layout, debug at the probe point, and separate PHY vs. package vs. board vs. firmware
• Scripting for lab automation and data analysis (Python preferred)
• Clear written and verbal communication; you can present a margin plot and a root-cause story to design and program teams.