On-Site PCIe SerDes Characterization Engineer - Palo Alto

Hikinex

Palo Alto (CA)

Sur place

USD 120 000 - 150 000

Temps partiel

Il y a 9 jours

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Résumé du poste

Hikinex is seeking a hands-on PCIe Characterization Engineer to perform post-silicon electrical characterization of high-speed SerDes interfaces in a lab. You will independently operate measurement equipment, analyze signal integrity, and automate workflows using Python.

The role emphasizes PCIe/SerDes validation, eye/jitter/BER/S-parameter measurements, and collaboration with silicon and systems teams. On-site in Palo Alto, CA.

Qualifications

  • 5+ years of post-silicon characterization or HSIO validation.
  • Hands-on SerDes PHY characterization experience.
  • Experience measuring eye diagrams, jitter, BER and S-Parameters.
  • Proficiency with high-speed test equipment (oscilloscopes, BERT, VNA/TDR).
  • Ability to read schematics and PCB layouts.
  • Python scripting for test automation.
  • Willingness to work on-site in Palo Alto, CA.

Responsabilités

  • Perform post-silicon electrical characterization of high-speed SerDes PHYs (PCIe, Ethernet, UFS, LPDDR5).
  • Support interface validation and investigate electrical performance issues.
  • Analyze results to assess high-speed interface performance and document findings.
  • Operate laboratory measurement equipment and troubleshoot signal integrity.
  • Develop and maintain Python scripts to automate measurements.

Connaissances

Post-silicon characterization
HSIO validation
PCIe SerDes
Python scripting
Schematic/PCB reading
Electrical debugging
Laboratory automation

Outils

High-speed oscilloscopes
BERT
VNA/TDR

Description du poste

Hikinex is seeking a hands-on PCIe Characterization Engineer to perform post-silicon electrical characterization of high-speed SerDes interfaces in a lab. You will independently operate measurement equipment, analyze signal integrity, and automate workflows using Python.

The role emphasizes PCIe/SerDes validation, eye/jitter/BER/S-parameter measurements, and collaboration with silicon and systems teams. On-site in Palo Alto, CA.

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