Senior Packaging Design Engineer

Platform Recruitment; Austin (TX); On-site; USD 200,000 - 400,000; Full time

Benefits offered by this job

Equity and stock options

Annual bonus

Living-local bonus

Job summary

Platform Recruitment in Austin, TX seeks a Senior/Staff Packaging Engineer to lead advanced ASIC packaging from architecture through production readiness, collaborating with ASIC, thermal, mechanical, and systems teams.

You will drive 2.5D/3D packaging architectures, SI/PI simulations, substrate-to-board integration, and establish package design methodologies. Compensation includes $200k–$400k salary with equity and annual bonus for the right candidate.

Qualifications

• Deep expertise in advanced semiconductor packaging for ASICs or high-performance products.
• Front-end package design and ASIC-to-substrate integration experience.
• Hands-on 2.5D/3D packaging architecture experience.

Responsibilities

• Lead advanced package design for ASIC-to-substrate integration including bump mapping and floorplanning.
• Develop 2.5D and 3D package architectures for multi-die designs.
• Own the package design flow from concept through manufacturing support.

Skills

Semiconductor packaging

Front-end package design

2.5D/3D packaging

CAD tools (Cadence Allegro)

SI/PI simulation

Package-to-board integration

Mentoring engineers

Manufacturing support

Education

Engineering or physical sciences degree

Tools

Cadence Allegro

Siemens Xpedition

Ansys SIwave

Cadence Sigrity

Job description

My client, an ambitious AI hardware company, is developing next-generation accelerators designed to improve the performance and efficiency of AI infrastructure. They are looking for a Senior / Staff Packaging Engineer to lead advanced ASIC packaging, from architecture and substrate design through simulation, integration and production readiness.

Key Responsibilities

• Lead advanced package design for ASIC-to-substrate integration, including bump mapping, substrate routing, floorplanning and stack-up definition
• Develop 2.5D and 3D package architectures for multi-die and chiplet-based designs
• Own the package design flow from concept and layout through simulation, verification, sign-off and manufacturing support
• Run package-level signal and power integrity (SI/PI) simulations to optimise performance and power delivery
• Drive substrate and PCB co-design, ensuring alignment between silicon, package and board-level interfaces
• Establish package design methodologies, libraries, workflows and implementation guidelines
• Collaborate with ASIC, thermal, mechanical and systems engineers, as well as substrate vendors and manufacturing partners
• Support prototype builds, qualification, failure analysis and productisation

Requirements

• Deep expertise in advanced semiconductor packaging for ASICs or other high-performance products
• Strong experience in front-end package design and ASIC-to-substrate integration
• Hands-on experience with 2.5D and/or 3D packaging architectures
• Proficiency with package design tools such as Cadence Allegro, Siemens Xpedition or equivalent
• Experience leading package development across layout, simulation, verification and release
• Strong PI/SI simulation experience using tools such as Ansys SIwave, Cadence Sigrity or equivalent
• Experience in substrate design and package-to-board integration
• Understanding of manufacturability, interconnect technologies and package reliability
• Relevant degree in engineering or physical sciences
• Experience with AI accelerators, HPC, networking or advanced data-centre hardware
• Familiarity with wafer-level packaging, package qualification and failure analysis
• Experience mentoring engineers and supporting new product introduction

What’s on Offer

• $200k–$400k salary, depending on experience
• Meaningful equity and stock options
• Annual living-local bonus for those residing within 20 minutes of the office
• Opportunity to shape advanced packaging technology for next-generation AI hardware