ASIC Package Engineer

Meta; Sunnyvale, Austin (CA, TX); On-site; USD 180,000 - 260,000; Full time

Job summary

Meta is seeking an experienced ASIC Package Engineer to own package-to-board attach processes for its AI/ML and networking silicon. You will lead development, qualification, and optimization of packaging interfaces, collaborating with PQE, SQE, and module design teams to deliver robust, high-yield manufacturing flows for data-center hardware.

Applicants should have 8+ years in semiconductor packaging, with strong experience in solder paste printing, reflow soldering, inspection, and DOE-based

Qualifications

• 8+ years of experience in semiconductor packaging with direct ownership of package-to-board assembly and reliability.
• Experience with package board technology processes including solder paste printing, pick-and-place, reflow soldering, and inspection methods.
• Experience working with package assembly and ODM suppliers and driving process qualification and yield improvement programs.
• Experience with failure analysis techniques for solder joint reliability and package-board interaction-related defects.
• Experience collaborating with quality engineering teams (PQE/SQE) to establish process controls and qualification requirements.

Responsibilities

• Lead development and optimization of package-to-board attach processes.
• Coordinate with Product Quality Engineering (PQE) and Supplier Quality Engineering (SQE) and design teams to establish qualified, high-yield packaging.
• Drive process qualification, DOE studies, and yield improvements across packaging technologies.

Skills

ASIC packaging

Package-to-board interaction

Statistical process control

Design of Experiments

Solder alloy selection

Thermo-mechanical analysis

AI/HPC hardware experience

Education

Bachelor's degree in Computer Science/Computer Engineering

Master's degree in Materials Science/Mechanical Engineering/Electrical Engineering

PhD in Materials Science/Mechanical Engineering or related

Tools

SPI inspection systems

AOI

X-ray inspection

Reflow soldering

Job description

Meta is looking for an experienced ASIC Package Engineer to join its ASIC Packaging team. This role owns the technology development and qualification readiness of the package-to-board attach process for Meta's custom AI/ML and networking silicon — the critical interface where a larger than reticle sized, large-body advanced package meets the motherboard Meta designs. The engineer will lead the development and optimization of package interaction with board attach processes. The Meta Infrastructure team designs, builds, brings up, tests, and integrates custom and general-purpose silicon-based hardware systems that power Meta's platforms, deployed in data centers worldwide. Designs are published through the Open Compute Project Foundation. We are building a deep competency in packaging technology to support the rapid development of custom silicon and to develop scalable packaging solutions that are optimal for our next-generation AI/ML products and system-level performance. As die sizes grow past 3.3x reticle and packages move to lidless/lidded and asymmetric stackups, board technology development for next gen ASIC is very important to achieve desired yield due to challenges with package warpage, thermo-mechanical stresses, and solder-joint reliability. The person in this role serves as the primary packaging expert for package to board technology development, working shoulder-to-shoulder with Product Quality Engineering (PQE), Supplier Quality Engineering (SQE), and module design teams to turn it into a fully qualified, statistically controlled, high-yield manufacturing process.

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• Master's degree in Materials Science, Mechanical Engineering, Electrical Engineering, or a related field, or equivalent practical experience
• 8+ years of experience in semiconductor packaging with direct ownership of package-to-board assembly and reliability; package-board interaction process engineering or electronics manufacturing background
• Experience with package board technology processes including solder paste printing, pick-and-place, reflow soldering, and inspection methods
• Experience working with package assembly and ODM suppliers and driving process qualification and yield improvement programs
• Experience with failure analysis techniques for solder joint reliability and package-board interaction-related defects
• Experience collaborating with quality engineering teams (PQE/SQE) to establish process controls and qualification requirements
• Experience with statistical process control, process capability analysis, and Design of Experiments
• Willingness to travel internationally, typically once per quarter
• Experience with reflow temperature profiling, solder alloy and paste material selection, and low-temperature solder processes
• Experience with AI/HPC or networking hardware at data-center scale
• Experience with high-temperature warpage characterization and thermo-mechanical or finite element modeling (FEM) of packages and solder joints
• Hands-on experience with SPI, AOI, and X-ray inspection systems and associated data analysis
• Experience with large-body FCBGA, flip-chip, and 2.5D/3D advanced packages and their interaction with board-assembly constraints
• Master's degree or PhD in Materials Science, Mechanical Engineering, or a related discipline
• Knowledge of packaging and assembly industry standards
• Experience with ODM, CM/EMS, OSAT, and substrate supplier engagement and audit