Hardware ASIC Packaging SI/PI Simulation and Design Lead (Remote)

Ladders; United States; Remote; USD 187,000 - 268,000; Full time

Benefits offered by this job

Medical, dental, and vision insurance

401(k) plan with matching contributors

Paid parental leave and short-term/lt>

Job summary

Ladders is seeking a Hardware ASIC Packaging SI/PI Simulation and Design Lead to guide signal and power integrity efforts for advanced ASIC packaging in a high-performance, high-volume hardware environment. You will partner with layout, architecture, and vendor teams to develop robust design rules and resolve complex technical issues.

This remote US-based role emphasizes mentoring engineers and driving continuous improvement across the organization, with compensation in the range of $186,900 to

Qualifications

• Bachelor's degree in Electrical Engineering with 8+ years' experience in SI/PI
• Experience with 56G PAM4 SerDes architectures
• Proficiency in Cadence Sigrity and Ansys HFSS for SI/PI simulations
• Layout reviews and physical validation with Cadence APD and Ansys EM
• SPICE-based circuit analysis and performance validation

Responsibilities

• Develop and implement design rules for ultra-high-speed signaling to meet power and performance goals
• Analyze substrate signal and power integrity, collaborating with layout teams for optimal solutions
• Design and document ASIC packages for high-volume release, including post-layout extraction
• Collaborate with system partners and vendors to resolve complex technical issues using advanced design rules
• Define processes and tools for complex ASIC/package developments
• Lead discussions on chip architecture and design of high-performance ASICs
• Mentor junior engineers and promote a culture of continuous improvement across engineering teams

Skills

Signal integrity

Power integrity

High-speed design

Leadership

Mentoring

Team collaboration

Education

Bachelor's degree in Electrical Engineering

Master's degree

PhD

Tools

Cadence Sigrity

Ansys HFSS

Cadence APD

Ansys EM

SPICE

Job description

For our client, we are seeking a Hardware ASIC Packaging SI/PI Simulation and Design Lead to join the team of a leader in the Telecommunications & Hardware space.

This role will guide signal and power integrity efforts for advanced ASIC packaging in a high-performance, high-volume hardware environment. The successful candidate will partner closely with layout, architecture, and vendor teams to develop robust design rules, resolve complex technical issues, and ensure package solutions meet performance and power targets. In addition to technical execution, this leader will help define processes and tools that support scalable development, while mentoring engineers and driving continuous improvement across the organization.

Location: Remote - US based candidates only, no visa sponsorship available

Compensation: $186,900 – $267,700 annually

Responsibilities

• Develop and implement design rules for ultra-high-speed signaling to meet power and performance goals


• Analyze substrate signal and power integrity, collaborating with layout teams for optimal solutions


• Design and document ASIC packages for high-volume release, including post-layout extraction


• Collaborate with system partners and vendors to resolve complex technical issues using advanced design rules


• Define processes and tools for complex ASIC/package developments


• Lead discussions on chip architecture and design of high-performance ASICs


• Mentor junior engineers and promote a culture of continuous improvement across engineering teams

Qualifications

• Bachelor's degree in Electrical Engineering with 8+ years of experience, or Master's with 6+ years, or PhD with 3+ years in signal and power integrity


• Proficient in high-speed design principles, including Transmission Line Theory and impedance network analysis for 56G PAM4 SerDes architectures


• Experienced in SI/PI simulations using tools like Cadence Sigrity and Ansys HFSS


• Skilled in conducting layout reviews and physical validation with Cadence APD and Ansys EM flows


• Familiar with SPICE for circuit-level analysis and performance validation

Benefits

• Medical, dental, and vision insurance


• 401(k) plan with matching contributions


• Paid parental leave and short-term/long-term disability coverage


• Flexible vacation time off for exempt employees


• Paid time off for holidays, personal wellness, and volunteer opportunities

Our client is an equal opportunity employer. We encourage you to apply even if you don’t meet every qualification—your background could be exactly what this team needs.