Packaging Architect

Platform Recruitment; Austin (TX); On-site; USD 400,000 - 600,000; Full time

Benefits offered by this job

Equity and stock options

Annual bonus

Career growth and leadership role

Job summary

Platform Recruitment seeks a Senior Packaging Architect in Texas to own advanced semiconductor packaging strategy and architecture for AI hardware accelerators. The role blends hands‑on design with long‑term roadmap ownership and cross‑functional leadership.

You will drive 2.5D/3D architectures, SI/PI analyses, and package‑to‑board co‑design while building a packaging engineering team. 10+ years in advanced packaging is expected, with strong vendor relationships and production experience.

Qualifications

• 10+ years in advanced semiconductor packaging for ASICs or high‑performance products.
• Ownership of package architecture, technology strategy or roadmap development.
• Deep expertise in ASIC-to-substrate integration and package design.
• Strong experience with 2.5D and/or 3D packaging, multi‑die integration and heterogeneous architectures.
• Hands‑on experience with Cadence Allegro X APD, Siemens Xpedition or equivalent tools.
• Strong package‑level SI/PI simulation skills using Ansys SIwave, Cadence Sigrity or equivalent.
• Experience across package layout, verification, release and package‑to‑board integration.
• Experience establishing packaging capabilities, processes or teams.
• Strong relationships with substrate vendors, OSATs and foundries.
• Experience with AI accelerators, HPC, networking or data‑centre hardware.
• Exposure to wafer‑level packaging and emerging advanced packaging technologies.
• Experience with optical or photonic integration.
• Knowledge of package reliability, qualification and failure analysis.
• Experience taking advanced packaging technologies into production.

Responsibilities

• Own ASIC-to-substrate package architecture, including bump mapping, substrate routing, floorplanning and stack‑up definition.
• Lead package design from concept through layout, simulation, verification, sign‑off and manufacturing release.
• Develop future 2.5D/3D architectures, including multi‑die, chiplet and heterogeneous integration.
• Lead package‑level signal integrity and power integrity analysis, translating results into design improvements.
• Drive package‑to‑board co‑design, aligning silicon, substrate, PCB and system requirements.
• Establish packaging design methodologies, libraries, tool flows and engineering processes.
• Build relationships with substrate vendors, OSATs, foundries and external manufacturing partners.
• Lead DFM, qualification, reliability and productisation activities.
• Help build and lead a packaging engineering team while remaining technically hands‑on.

Skills

Package architecture

ASIC-to-substrate

2.5D/3D packaging

SI/PI simulation

Cadence Allegro

Ansys SIwave

Cadence Sigrity

Vendor relations

Tools

Cadence Allegro

Siemens Xpedition

Ansys SIwave

Cadence Sigrity

Job description

My client, an ambitious AI hardware company developing next‑generation accelerators, is looking for a Packaging Architect to own its advanced semiconductor packaging strategy and architecture. This is a senior, hands‑on role combining package design and simulation with long-term technology roadmap ownership, cross‑functional collaboration and the opportunity to build a packaging engineering team.

Key Responsibilities

• Own ASIC-to-substrate package architecture, including bump mapping, substrate routing, floorplanning and stack‑up definition
• Lead package design from concept through layout, simulation, verification, sign‑off and manufacturing release
• Develop future 2.5D/3D architectures, including multi‑die, chiplet and heterogeneous integration
• Lead package‑level signal integrity and power integrity analysis, translating results into design improvements
• Drive package‑to‑board co‑design, aligning silicon, substrate, PCB and system requirements
• Establish packaging design methodologies, libraries, tool flows and engineering processes
• Build relationships with substrate vendors, OSATs, foundries and external manufacturing partners
• Lead DFM, qualification, reliability and productisation activities
• Help build and lead a packaging engineering team while remaining technically hands‑on

Requirements

• 10+ years' experience in advanced semiconductor packaging for ASICs or high‑performance products
• Proven ownership of package architecture, technology strategy or roadmap development
• Deep expertise in ASIC-to-substrate integration and package design
• Strong experience with 2.5D and/or 3D packaging, multi‑die integration and heterogeneous architectures
• Hands‑on experience with Cadence Allegro X APD, Siemens Xpedition or equivalent tools
• Strong package‑level SI/PI simulation skills using Ansys SIwave, Cadence Sigrity or equivalent
• Experience across package layout, verification, release and package‑to‑board integration
• Experience establishing packaging capabilities, processes or teams
• Strong relationships with substrate vendors, OSATs and foundries
• Experience with AI accelerators, HPC, networking or data‑centre hardware
• Exposure to wafer‑level packaging and emerging advanced packaging technologies
• Experience with optical or photonic integration
• Knowledge of package reliability, qualification and failure analysis
• Experience taking advanced packaging technologies into production

What's on Offer

• $400,000-$600,000 base salary, depending on experience
• Meaningful equity and stock options
• Annual living-local bonus for employees living within 20 minutes of the office
• Strategic ownership of packaging architecture and future technology direction
• Opportunity to build a packaging function and team from the ground up
• Work on next‑generation AI accelerator technology at the forefront of hardware innovation