Senior Package Layout Engineer for AI Accelerators

Acceler8 Talent; Mountain View (CA); Vor Ort; USD 180.000 - 250.000; Vollzeit

Benefits dieser Stelle

401(k)

Dental insurance

Vision insurance

Medical insurance

Zusammenfassung

Acceler8 Talent is seeking a seasoned Package Layout Engineer in Mountain View, CA. This role is onsite and focuses on owning the end-to-end physical design of advanced semiconductor packages for AI accelerators, including 2.5D/3D stackups, bump mapping, and interposer routing.

You will work with silicon, SI/PI, PCB, and packaging teams to deliver high-performance packages, drive co-design with OEM partners, and ensure manufacturing readiness through DRC/LVS verification and signoff.

Qualifikationen

• 8+ years of professional semiconductor package layout experience.
• Expertise in 2.5D/3D packaging and multi-die integration technologies.
• Hands-on experience with package substrate and interposer layout and high-density routing.
• Strong understanding of package stackup, bump mapping, vias, and power/ground plane design.
• Experience with package verification (DRC/LVS) and signoff.

Aufgaben

• Own end-to-end package substrate and interposer layout with stackup definition and final design release.
• Design and optimize multi-die 2.5D/3D packages supporting high-bandwidth memory interfaces.
• Develop package power and ground distribution networks for high-current accelerators.
• Collaborate with silicon, PI, PCB, and OSAT teams for co-design and manufacturing readiness.
• Perform package DRC/LVS verification and netlist checks.
• Coordinate with OSAT partners and substrate suppliers to meet manufacturing requirements.
• Address routing, signal integrity, and manufacturability challenges.
• Leverage AI-assisted design tools to accelerate layout and verification processes.

Kenntnisse

Semiconductor packaging

2.5D/3D packaging

RDL design

Cadence tools

OSAT collaboration

Tools

Cadence Allegro Package Designer

Cadence SiP Layout

Siemens Xpedition Package Designer

Jobbeschreibung

Acceler8 Talent is seeking a seasoned Package Layout Engineer in Mountain View, CA. This role is onsite and focuses on owning the end-to-end physical design of advanced semiconductor packages for AI accelerators, including 2.5D/3D stackups, bump mapping, and interposer routing.

You will work with silicon, SI/PI, PCB, and packaging teams to deliver high-performance packages, drive co-design with OEM partners, and ensure manufacturing readiness through DRC/LVS verification and signoff.