Senior Optical Receiver Analog/Mixed-Signal Engineer

Octopyd; Sunnyvale (CA); On-site; USD 180,000 - 280,000; Full time

Job summary

Avicena in Sunnyvale, CA seeks a Senior/Principal Analog Mixed-Signal Design Engineer for the Optical Receiver. You will own the receiver front-end from spec to signoff, turning photodetector current into clean data across many parallel lanes, collaborating with RX, layout and digital teams.

Role spans senior through principal levels; title and scope match experience. You will lead reviews, mentor engineers, and drive architecture trade-offs while delivering robust silicon.

Qualifications

• MS or PhD in Electrical Engineering or BS with equivalent experience.
• 5+ years of analog/mixed-signal design experience.
• Taped-out high-speed receiver circuits such as TIAs and CTLEs.
• Design experience in FinFET or advanced CMOS processes.
• Proficiency with Cadence Virtuoso and Spectre for analysis.

Responsibilities

• Design and simulate receiver circuits: photodetector interface and transimpedance amps.
• Analyze noise, bandwidth, sensitivity, crosstalk and power per lane across corners.
• Design calibration and trim circuits with digital team interfaces.
• Collaborate with layout for floorplans, routing, and post-layout verification.
• Provide behavioral models and correlate with transistor-level results.
• Write block specifications and present at design reviews.
• Support silicon bring-up and correlate measurements with simulation.
• At principal level: set technical direction and lead reviews; mentor engineers.

Skills

Analog/mixed-signal design

Noise analysis

Verilog-A / SystemVerilog real-number

MATLAB or Python

Mentoring engineers

Block specification

Education

MS/PhD in Electrical Engineering

BS with equivalent experience

Tools

Cadence Virtuoso

Spectre

Job description

Avicena in Sunnyvale, CA seeks a Senior/Principal Analog Mixed-Signal Design Engineer for the Optical Receiver. You will own the receiver front-end from spec to signoff, turning photodetector current into clean data across many parallel lanes, collaborating with RX, layout and digital teams.

Role spans senior through principal levels; title and scope match experience. You will lead reviews, mentor engineers, and drive architecture trade-offs while delivering robust silicon.