Senior Analog/Mixed-Signal IC Design for Optical TX/RX

Langham Recruitment; San Jose (CA); On-site; USD 150,000 - 300,000; Full time

Benefits offered by this job

Healthcare

401(k)

Paid leave

Job summary

Langham Recruitment is seeking a Senior Analog & Mixed-Signal Design Engineer in San Jose, CA to advance high-speed optical interconnects. You will work on 100G-per-lane transceivers, including EIC/PIC integration and link-budget definition, in collaboration with photonics and DSP teams.

We expect expertise in high-speed analog CMOS, SerDes designs, and silicon photonics familiarity. Cadence, MATLAB, and Python are key tools; a PhD or MS in a related field is preferred.

Qualifications

• MS or PhD in Electrical Engineering, Applied Physics or a related field.
• Strong high-speed analog CMOS design experience in advanced process nodes.
• Experience with SerDes, wireline transceivers or optical transceiver design.
• Familiarity with silicon photonics and electro-optic devices (MZMs, MRMs, EAMs, photodetectors).
• Proficiency with Cadence, mixed-signal simulation, and MATLAB or Python.

Responsibilities

• Develop architectures for high-speed SerDes and optical transceivers, including EIC/PIC integration and link-budget definition.
• Design and verify high-performance analog and mixed-signal circuits (modulator drivers, TIAs, ADCs/DACs, PLLs, CDRs, clocking).
• Model electro-optic systems and photonic components using MATLAB, Python or Verilog-A.
• Collaborate with photonics, DSP, packaging and SI teams to optimize performance and integration.
• Support silicon bring-up, lab testing, debugging and post-silicon validation through to production.

Skills

High-speed analog CMOS

SerDes / optical transceivers

Electro-optic design

Cadence tooling

MATLAB / Python

Education

MS or PhD in Electrical Engineering or Applied Physics

Tools

Cadence

MATLAB

Python

Verilog-A

Lumerical

Job description

Langham Recruitment is seeking a Senior Analog & Mixed-Signal Design Engineer in San Jose, CA to advance high-speed optical interconnects. You will work on 100G-per-lane transceivers, including EIC/PIC integration and link-budget definition, in collaboration with photonics and DSP teams.

We expect expertise in high-speed analog CMOS, SerDes designs, and silicon photonics familiarity. Cadence, MATLAB, and Python are key tools; a PhD or MS in a related field is preferred.