Hybrid Senior ASIC Verification Engineer – Networking

Hewlett Packard Enterprise Company in; Sunnyvale (CA); Hybrid; USD 174,000 - 353,000; Full time

Benefits offered by this job

Health benefits

Career development programs

Inclusive culture

Job summary

Hewlett Packard Enterprise in Sunnyvale, CA is seeking a Senior ASIC Verification Engineer for a hybrid role requiring 2 days per week in the office. You will own block- or subsystem-verification efforts, build and maintain UVM environments, and drive coverage closure for complex SoCs.

Ideal candidates bring strong SystemVerilog/UVM skills, extensive ASIC/SoC verification experience, and proficiency with Cadence Xcelium, Synopsys VCS, and Mentor Questa.

Qualifications

• 15+ years of experience in ASIC/SoC verification.
• Strong expertise in SystemVerilog and UVM.
• Knowledge of coverage analytics, constraints, randomization, and assertions (SVA).
• Hands-on test planning, coverage analysis, and debugging of complex SoC designs.
• Proficiency with Cadence Xcelium, Synopsys VCS, Mentor Questa and waveform debugging.

Responsibilities

• Own and drive block-level or subsystem verification efforts from test plans to coverage closure.
• Develop, enhance, and maintain advanced UVM verification environments (agents, sequences, scoreboards, registers).
• Perform constraint-driven random testing and debug complex SoC designs to meet coverage goals.
• Analyze simulation results with industry tools and debug waveforms to validate functionality.
• Collaborate with cross-functional teams to ensure high-quality ASIC/SoC deliverables.

Skills

SystemVerilog

UVM

SoC Verification

Test Planning

Debugging

Tools

Cadence Xcelium

Synopsys VCS

Mentor Questa

Job description

Hewlett Packard Enterprise in Sunnyvale, CA is seeking a Senior ASIC Verification Engineer for a hybrid role requiring 2 days per week in the office. You will own block- or subsystem-verification efforts, build and maintain UVM environments, and drive coverage closure for complex SoCs.

Ideal candidates bring strong SystemVerilog/UVM skills, extensive ASIC/SoC verification experience, and proficiency with Cadence Xcelium, Synopsys VCS, and Mentor Questa.