Senior Network ASIC Verification Engineer

Broadcom; San Jose (CA); On-site; USD 120,000 - 192,000; Full time

Benefits offered by this job

Discretionary annual bonus

Equity grants

Equity awards

Medical/dental/vision plans

401(k) with company match

Employee stock purchase program (ESPP)

Paid holidays

Paid sick leave and vacation

Job summary

The CSG group at Broadcom is developing Tomahawk ASICs for scale-out AI networks, with high-throughput switching and multi-chip solutions. The successful candidate will verify L2/L3 network switching designs, create test plans, and build verification environments and testbenches to enable pre-silicon validation.

Candidates should have a MSEE/BSEE with 8+ years in digital design verification, hands-on Verilog/SystemVerilog/UVM experience, scripting in Perl/Python, and strong communication skills.

Qualifications

• BS/MS/PhD with digital design and verification focus and strong academics.
• Experience with Verilog/SystemVerilog/UVM and scripting (Perl, Python).
• End-to-end ASIC/SOC verification experience from test plan to coverage closure.
• Excellent verbal and written communication skills.

Responsibilities

• Participate in verification of L2/L3 Network Switching ASICs and subsystems.
• Develop test plans for L2/L3 traffic features and performance characterization.
• Create verification environments with testbenches and APIs for chip architecture.
• Implement tests in SystemVerilog and execute pre-silicon verification with coverage metrics.
• Run scripts and Makefiles to operate environments across toolchains.

Skills

SystemVerilog/UVM

Perl

Python

OOP

Verilog/SystemVerilog/UVM

Strong communication

Education

MSEE or BSEE or equivalent

8+ years in digital design verification

Tools

Verilog/SystemVerilog/UVM

Perl

Python

Job description

The CSG group at Broadcom is developing Tomahawk ASICs for scale-out AI networks, with high-throughput switching and multi-chip solutions. The successful candidate will verify L2/L3 network switching designs, create test plans, and build verification environments and testbenches to enable pre-silicon validation.

Candidates should have a MSEE/BSEE with 8+ years in digital design verification, hands-on Verilog/SystemVerilog/UVM experience, scripting in Perl/Python, and strong communication skills.