Design Verification Engineer

Broadcom; San Jose (CA); On-site; USD 120,000 - 192,000; Full time

Benefits offered by this job

Discretionary annual bonus

Equity grants

Equity awards

Medical/dental/vision plans

401(k) with company match

Employee stock purchase program (ESPP)

Paid holidays

Paid sick leave and vacation

Job summary

The CSG group at Broadcom is developing Tomahawk ASICs for scale-out AI networks, with high-throughput switching and multi-chip solutions. The successful candidate will verify L2/L3 network switching designs, create test plans, and build verification environments and testbenches to enable pre-silicon validation.

Candidates should have a MSEE/BSEE with 8+ years in digital design verification, hands-on Verilog/SystemVerilog/UVM experience, scripting in Perl/Python, and strong communication skills.

Qualifications

• BS/MS/PhD with digital design and verification focus and strong academics.
• Experience with Verilog/SystemVerilog/UVM and scripting (Perl, Python).
• End-to-end ASIC/SOC verification experience from test plan to coverage closure.
• Excellent verbal and written communication skills.

Responsibilities

• Participate in verification of L2/L3 Network Switching ASICs and subsystems.
• Develop test plans for L2/L3 traffic features and performance characterization.
• Create verification environments with testbenches and APIs for chip architecture.
• Implement tests in SystemVerilog and execute pre-silicon verification with coverage metrics.
• Run scripts and Makefiles to operate environments across toolchains.

Skills

SystemVerilog/UVM

Perl

Python

OOP

Verilog/SystemVerilog/UVM

Strong communication

Education

MSEE or BSEE or equivalent

8+ years in digital design verification

Tools

Verilog/SystemVerilog/UVM

Perl

Python

Job description

USA-CA San Jose Innovation Drive

Full time

R025763

Job Description:

The CSG group at Broadcom has brought some of the most complex and cutting edge networking ASIC's and multichip solutions to market over the last decade. The group

develops Tomahawk ASICs for Scale-Out and Scale-Up AI Networks. These products support the latest networking protocols and features as well as manage extremely large volumes of traffic of the order of several hundreds of Terabits/sec. These networking ASIC's support a large number of ports ranging from 10/100Mb/s to 1600Gb/s speeds as well as various line interfaces and protocols.

The successful candidate will be responsible for various key tasks in the areas of verification of cutting edge network switch routing designs. The daytoday tasks for this position include but are not limited to the following:

• Participating in the verification processes of L2/L3 Network Switching and routing ASICs and various subsystems within these chips
• Understanding the architecture and implementation of these chips and coming up with in depth test plans for verifying various key networking features such as L2/L3 traffic streaming, traffic management, scheduling and shaping of traffic, latency and performance characterization of chips and systems.
• Developing verification environments including testbenches and verification API’s associated with the chip architecture to enable testing of various features within the chips as well as scripts and Makefiles as required to run the environment in various tool chains
• Implementing test plans into executable test suites using a cutting edge Systemverilog verification environment.
• Executing the verification process to completion pre-silicon using various functional and code coverage metrics as measures of completion

The successful candidate will satisfy the following requirements:

• MSEE or BSEE or equivalent, with concentration in digital design and excellent academic standing. Total engineering minimum experience required is typically a BS degree and 8years of experience, an MS degree and 6+ years of experience or a PhD and 3+ years of experience or equivalent.
• Familiar with Hardware description languages (Verilog/SystemVerilog/UVM), scripting languages (Perl, Python) and Object Oriented Programming (OOP).
• Exposure to cutting edge verification and validation techniques and methodologies using Object Oriented modular reusable environments in languages such as Systemverilog,
  Perl, Python
• Strong understand and prior experience of end-to-end verification process from test plan definition to coverage closure on ASIC/SOC silicon that has gone into mass production
• Excellent verbal and written communication skills.

Additional Job Description:

Compensation and Benefits

The annual base salary range for this position is $120,000 - $192,000

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

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