Senior Modem PHY IP Verification Engineer

Blue Origin; Van Horn (TX); On-site; USD 269,175 - 376,843; Full time

Benefits offered by this job

Medical insurance

Dental insurance

Vision insurance

401(k) match

Paid time off

Stock options

Education support

Job summary

Blue Origin is seeking an experienced Principal Modem PHY IP Design Verification Engineer to lead verification of advanced modem PHY IP for the Terawave program. The role centers on building scalable verification environments, developing testbenches, and ensuring robust delivery across simulation, emulation, prototyping, and silicon bring-up.

The ideal candidate combines strong DSP/PHY knowledge with SystemVerilog and UVM expertise, collaborating with RTL, firmware, FPGA, and validation teams in

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field.
• 10+ years of experience in digital design verification, ASIC/SoC verification, or modem/baseband verification.
• Strong experience with SystemVerilog and modern verification methodologies such as UVM.
• Experience developing verification environments for complex DSP, modem, or communications IP.
• Familiarity with one or more of the following modem PHY areas: OFDM/single-carrier, synchronization, channel estimation/equalization, LDPC/Polar/Turbo/BCH, MIMO/beamforming, fixed-point/quantized processing.
• Experience with scripting and automation using Python, Perl, shell, or similar tools.
• Strong debugging and problem-solving skills across RTL, testbench, and model correlation issues.
• Ability to work closely with design, architecture, and systems teams in a fast-paced development environment.

Responsibilities

• Develop and execute verification strategy and plans for modem PHY IP and subsystem-level integration.
• Build and maintain block-level and subsystem-level verification environments for PHY IP using industry-standard methodologies.
• Create testbenches, stimulus, checkers, scoreboards, assertions, and coverage models to verify modem PHY functionality and corner cases.
• Verify key PHY IP functions such as modulation/demodulation, timing/frequency synchronization, channel estimation/equalization, MIMO/beamforming, FEC integration, and interfaces.
• Collaborate with PHY algorithm and architecture teams to correlate RTL behavior against reference models.
• Define and track functional, code, assertion, and scenario coverage for verification completeness.
• Develop constrained-random and directed test strategies for feature, stress, and corner-case validation.
• Identify, debug, and root-cause design and integration issues in collaboration with RTL and architecture teams.
• Support verification of performance-sensitive designs with attention to throughput, latency, buffering, and protocol timing behavior.
• Contribute to regression automation, CI flows, and verification infrastructure improvements.
• Support subsystem integration, FPGA prototyping, emulation, and post-silicon debug as needed.
• Document verification plans, test results, coverage status, and quality metrics.
• Work effectively with internal engineering teams and external design service partners to drive verification closure.

Skills

Debugging

Problem solving

Team collaboration

Fast-paced environment

Verification methodology

Education

Bachelor's degree in Electrical Eng./CS/related field

Tools

SystemVerilog

UVM

Python

Perl

Shell

Job description

Blue Origin is seeking an experienced Principal Modem PHY IP Design Verification Engineer to lead verification of advanced modem PHY IP for the Terawave program. The role centers on building scalable verification environments, developing testbenches, and ensuring robust delivery across simulation, emulation, prototyping, and silicon bring-up.

The ideal candidate combines strong DSP/PHY knowledge with SystemVerilog and UVM expertise, collaborating with RTL, firmware, FPGA, and validation teams in