Senior Modem PHY IP Verification Architect

Blue Origin; San Diego (CA); Presencial; USD 269.175 - 376.843; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Medical, dental, vision

Stock options

401(k)

Paid time off

Parental leave

Descripción de la vacante

Blue Origin LLC invites applications for a Principal Modem PHY IP Design Verification Engineer to lead verification for Terawave modem PHY IP. You will craft verification strategies and build scalable environments, ensuring accurate RTL behavior across simulation, emulation, and silicon bring-up.

The role requires 10+ years in digital verification, strong SystemVerilog/UVM skills, and experience with DSP/modem IP.

Formación

• 10+ years in digital design verification, ASIC/SoC or modem/baseband verification.
• Strong SystemVerilog and UVM experience with modern verification methodologies.
• Experience building verification environments for complex DSP/modem IP.
• Familiarity with OFDM, synchronization, channel estimation, MIMO/beamforming.

Responsabilidades

• Develop and execute verification strategy and plans for modem PHY IP.
• Build block- and subsystem-level verification environments.
• Create testbenches, stimuli, checkers, scoreboards, and coverage models.
• Collaborate with RTL/architecture teams to compare RTL against reference models.
• Support regression automation, CI flows, and post-silicon validation.

Conocimientos

SystemVerilog

UVM

DSP experience

Python

Scripting (Perl, shell)

Debugging

Verification planning

Educación

Bachelor's degree in Electrical/Computer Eng or related

Master's degree (preferred)

Herramientas

MATLAB

C/C++

Python

Descripción del empleo

Blue Origin LLC invites applications for a Principal Modem PHY IP Design Verification Engineer to lead verification for Terawave modem PHY IP. You will craft verification strategies and build scalable environments, ensuring accurate RTL behavior across simulation, emulation, and silicon bring-up.

The role requires 10+ years in digital verification, strong SystemVerilog/UVM skills, and experience with DSP/modem IP.