Lead Modem PHY IP Verification Architect

Blue Origin; San Diego (CA); On-site; USD 269,175 - 376,843; Full time

Benefits offered by this job

Medical, dental, vision

401(k) with company match

Stock options

Paid time off

Education Support Program

Job summary

Blue Origin seeks a Principal Modem PHY IP Design Verification Engineer to lead verification of advanced modem PHY IP for the Terawave program. You will develop robust verification strategies, build scalable environments, and ensure high-quality modem IP delivery across simulation, emulation, prototyping, and silicon bring-up phases.

The role requires strong SystemVerilog and UVM experience, collaboration with RTL, firmware, FPGA, and validation teams, and a focus on throughput, timing, and

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field.
• 10+ years of experience in digital design verification, ASIC/SoC verification, or modem/baseband verification.
• Strong experience with SystemVerilog and modern verification methodologies such as UVM.
• Experience developing verification environments for complex DSP, modem, or communications IP.
• Familiarity with modem PHY areas: OFDM, synchronization, channel estimation, FEC, MIMO/beamforming.

Responsibilities

• Develop and execute verification strategy and plans for modem PHY IP and subsystem-level integration.
• Build and maintain block-level and subsystem-level verification environments for PHY IP using industry-standard methodologies.
• Create testbenches, stimulus, checkers, scoreboards, assertions, and coverage models to verify modem PHY functionality and corner cases.
• Collaborate with PHY algorithm and architecture teams to correlate RTL behavior against reference models.
• Define and track functional, code, assertion, and scenario coverage to ensure verification closure.
• Develop constrained-random and directed test strategies for feature, stress, and corner-case validation.
• Identify, debug, and root-cause design and integration issues with RTL and architecture teams.
• Support verification of performance-sensitive designs with throughput, latency, buffering, and protocol timing behavior.
• Document verification plans, test results, coverage status, and quality metrics.

Skills

SystemVerilog

UVM

Python

C/C++

RTL debugging

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field

Job description

Blue Origin seeks a Principal Modem PHY IP Design Verification Engineer to lead verification of advanced modem PHY IP for the Terawave program. You will develop robust verification strategies, build scalable environments, and ensure high-quality modem IP delivery across simulation, emulation, prototyping, and silicon bring-up phases.

The role requires strong SystemVerilog and UVM experience, collaboration with RTL, firmware, FPGA, and validation teams, and a focus on throughput, timing, and