Senior Modem PHY IP Architect for High-Performance ASICs

Blue Origin; Van Horn (TX); On-site; USD 200,000 - 320,000; Full time

Job summary

Blue Origin is seeking a Principal Modem PHY IP Design Engineer to drive the PHY IP for the Terawave program. You will shape architecture, modeling, implementation, and validation of modem PHY functions for high-performance wireless ASIC solutions.

The role requires translating algorithms into hardware-oriented architectures and collaborating with systems, RTL, verification, FPGA, firmware, and validation teams to deliver robust PHY IP across FPGA prototypes and silicon.

Qualifications

• 10+ years of experience in wireless communications or modem PHY design and DSP.
• Proficiency in translating algorithms into hardware-oriented architectures.
• Experience with OFDM, synchronization, channel estimation, MIMO/beamforming, and FEC.
• Proficiency with MATLAB, Python, C/C++ for modeling and simulation.

Responsibilities

• Design and develop modem PHY IP for Terawave ASIC and prototyping platforms.
• Translate system and link requirements into implementation-ready PHY block specifications.
• Develop floating-point, fixed-point, and bit-accurate models for modem PHY functions.
• Perform performance analysis and trade studies across throughput, latency, area, and power.
• Collaborate with verification teams to define test strategies, reference models, and coverage plans.

Skills

Wireless communications

Modem PHY design

DSP

ASIC/FPGA

MATLAB

Python

C/C++

Education

Bachelor's degree in Electrical Engineering or related field

Job description

Blue Origin is seeking a Principal Modem PHY IP Design Engineer to drive the PHY IP for the Terawave program. You will shape architecture, modeling, implementation, and validation of modem PHY functions for high-performance wireless ASIC solutions.

The role requires translating algorithms into hardware-oriented architectures and collaborating with systems, RTL, verification, FPGA, firmware, and validation teams to deliver robust PHY IP across FPGA prototypes and silicon.