Senior ML Compiler & Model Bring-Up Engineer

General Compute; San Francisco (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

General Compute in San Francisco seeks a senior IC to bring up new models on our ASIC. You will own the end-to-end process from reference weights to first correct tokens, collaborating with the hardware partner to ensure correctness and performance.

You will build the agentic bringup loop, verify via diffs and parity checks, and optimize after correctness with fusion, quantization, and memory layout for production-ready models.

Qualifications

• 5+ years in systems or ML systems, with real depth in at least one of: ML compilers, model porting/bringup, or high-performance kernels.
• Strong on the internals of modern LLM inference: transformers, attention, KV cache, MoE routing, quantization, batching.
• Fluent with agentic tooling and self-directed work style.
• Comfortable inside a compiler stack — MLIR/LLVM, XLA, or a vendor graph compiler.

Responsibilities

• Own model bringup end-to-end. Take a new architecture from reference weights to first correct tokens running on our ASIC, in days, not quarters.
• Build the agentic bringup loop harness that compiles, runs, diffs against reference, and locates failing ops.
• Live in the compiler space: graph capture, IR lowering, op coverage, kernel selection when a model won’t compile or numbers are off.
• Own correctness before speed; build verification harness with layer-by-layer diffs, logit parity, end-to-end evals.
• Then optimize: operator fusion, quantization, memory layout, batching and KV-cache behavior for our hardware.
• Collaborate shoulder-to-shoulder with hardware partner’s compiler and runtime team to ship production-grade models.

Skills

ML systems

Model bringup

High-performance kernels

Transformers internals

KV cache

MoE routing

Quantization

Agentic tooling

Self-directed

Compiler stacks

Tools

MLIR/LLVM

XLA

CUDA

Triton

TensorRT-LLM

TVM

vLLM

TGI

Job description

General Compute in San Francisco seeks a senior IC to bring up new models on our ASIC. You will own the end-to-end process from reference weights to first correct tokens, collaborating with the hardware partner to ensure correctness and performance.

You will build the agentic bringup loop, verify via diffs and parity checks, and optimize after correctness with fusion, quantization, and memory layout for production-ready models.