Senior AI/SoC Modeling Engineer - High-Impact Pre-Silicon

Amazon Web Services (AWS); Austin (TX); On-site; USD 168,000 - 227,000; Full time

Job summary

Annapurna Labs (U.S.) Inc. in Austin, TX is seeking a Modeling Engineer to build and own high-fidelity C++/SystemC models of AI/ML accelerators and subsystems.

You will translate architecture specs into testable models and drive verification through pre-silicon validation environments. You'll collaborate with DV teams, architects, and RTL engineers to explore architectural tradeoffs and improve model fidelity.

Qualifications

• 6+ years of full software development life cycle experience, including reviews, CI and build processes.
• Mentoring or tech-lead experience in engineering teams.
• 6+ years writing functional or performance models of hardware (SoCs, ASICs, GPUs, CPUs, IP blocks).
• Proficient in C++ with knowledge of modern language features.
• Knowledge of SoC/CPU/GPU/ASIC architecture and micro-architecture.

Responsibilities

• Develop and maintain high-fidelity functional models of AI/ML accelerators and SoC subsystems in C++/SystemC.
• Validate model behavior against RTL simulations, emulation, or silicon measurements.
• Collaborate with DV teams to integrate models into pre-silicon validation environments.
• Evaluate architecture/microarchitecture tradeoffs with architects and RTL engineers.
• Contribute to cycle-approximate performance models for architectural exploration.
• Quantify system-level tradeoffs across compute, memory, networking, and storage.
• Build and improve modeling infrastructure and regression suites.
• Develop scalable modeling methodologies across IP blocks and SoC generations.

Skills

C++ modeling

SoC modeling

SystemC

Model verification

Multi-threaded sim

Architectural modeling

Tools

SystemC

TLM

CI regression

Regression frameworks

Job description

Annapurna Labs (U.S.) Inc. in Austin, TX is seeking a Modeling Engineer to build and own high-fidelity C++/SystemC models of AI/ML accelerators and subsystems.

You will translate architecture specs into testable models and drive verification through pre-silicon validation environments. You'll collaborate with DV teams, architects, and RTL engineers to explore architectural tradeoffs and improve model fidelity.