Senior ML Accelerator DV Engineer

Amazon; Cupertino (CA); On-site; USD 183,000 - 248,000; Full time

Benefits offered by this job

Health insurance

RSUs & sign-on

401(k) matching

Job summary

Amazon’s Machine Learning Acceleration team in Cupertino seeks a skilled Design Verification Engineer to verify SOCs for Inferentia and Trainium, collaborating across teams to optimize silicon yield and performance. You will contribute to testbenches, coverage plans, and robust debugging in a high-throughput data center environment.

The role requires strong SystemVerilog/UVM expertise, hands-on testbench development, and experience with C/C++ and Python.

Qualifications

• Bachelor's degree or above in Computer Science, Computer Engineering, Electrical Engineering, or related fields.
• 8+ years of design verification experience using SystemVerilog and UVM.
• 8+ years of testbench development including stimulus, checkers, assertions and coverage.

Responsibilities

• Verify custom chip designs at the SOC level.
• Integrate 3rd party IPs and VIPs into the SOC testbench.
• Create comprehensive testplans, write robust random testcases, and execute coverage plans.
• Maintain autosmoke and regression infrastructure.
• Dive deep into bugs and triages.
• Mentor junior engineers.

Skills

SystemVerilog

UVM

C/C++

Python

Object-Oriented

Debugging

Education

Bachelor's degree or above in CS/CE/EE

Tools

UVM test bench

FPGA

Emulator

Software environments

System testing

Job description

Amazon’s Machine Learning Acceleration team in Cupertino seeks a skilled Design Verification Engineer to verify SOCs for Inferentia and Trainium, collaborating across teams to optimize silicon yield and performance. You will contribute to testbenches, coverage plans, and robust debugging in a high-throughput data center environment.

The role requires strong SystemVerilog/UVM expertise, hands-on testbench development, and experience with C/C++ and Python.