Senior ML Accelerator Verification Engineer

Amazon Web Services (AWS); Austin (TX); In loco; USD 159.000 - 215.000; Tempo pieno

Descrizione del lavoro

Annapurna Labs (U.S.) Inc. in Austin, TX, is seeking an experienced Design Verification Engineer to help design and verify next‑generation server silicon for AWS.

You will verify SOC level designs, integrate IPs, create test plans, and maintain regression infrastructure while mentoring junior engineers. Applicants should have a strong background in SystemVerilog/UVM, extensive testbench development, and experience with AMBA, PCIe/UCIe, and memory subsystems.

Competenze

• Bachelor's degree or above in Computer Science, Computer Engineering, Electrical Engineering, or related fields.
• 8+ years of design verification experience using System Verilog and UVM.
• 8+ YOE in testbench development including: stimulus, checkers, assertions and coverage.

Mansioni

• Verify custom chip designs at the SOC level
• Integrate 3rd party IPs and VIPs into the SOC testbench
• Create comprehensive testplans, write robust random testcases, and execute coverage plans
• Maintain autosmoke and regression infrastructure
• Dive deep into bugs and triages
• Mentor junior engineers

Conoscenze

SystemVerilog

UVM

Testbench development

C/C++

Object-Oriented Programming

Python

ML accelerator verifications

Formazione

Bachelor's degree or above in Computer Science, Computer Engineering, Electrical Engineering, or related fields

Strumenti

UVM test bench

FPGA

emulator

AMBA protocols

PCIe/UCIe

Memory subsystems

Descrizione del lavoro

Annapurna Labs (U.S.) Inc. in Austin, TX, is seeking an experienced Design Verification Engineer to help design and verify next‑generation server silicon for AWS.

You will verify SOC level designs, integrate IPs, create test plans, and maintain regression infrastructure while mentoring junior engineers. Applicants should have a strong background in SystemVerilog/UVM, extensive testbench development, and experience with AMBA, PCIe/UCIe, and memory subsystems.