Senior DV Engineer – Cloud-Scale ML Accelerator SOC

Amazon; Austin (TX); On-site; USD 140,000 - 190,000; Full time

Job summary

Amazon is seeking experienced Design Verification Engineers for the MLA team to design and optimize custom silicon for cloud AI workloads. You will verify SOC designs, integrate IPs, and develop comprehensive test plans and testbenches for Inferentia/Trainium chips in AWS data centers.

You will work with multiple verification platforms, use SystemVerilog/UVM, and mentor junior engineers while contributing to silicon yield and performance improvements on a global scale.

Qualifications

• 8+ years of design verification experience using SystemVerilog and UVM.
• 8+ years of YOE in testbench development including stimulus, checkers, assertions and coverage.
• Experience verifying multiple levels of design including custom blocks, IP blocks, subsystems, and full-SoC testing.
• Experience with multiple verification platforms and scripting languages.

Responsibilities

• Verify custom chip designs at the SOC level.
• Integrate 3rd party IPs and VIPs into the SOC testbench.
• Create comprehensive test plans, write robust random testcases, and execute coverage plans.
• Maintain autosmoke and regression infrastructure.
• Dive deep into bugs and triages.
• Mentor junior engineers.

Skills

SystemVerilog

UVM

Testbench development

C/C++

Python scripting

Education

Bachelor's degree or higher in CS/CE/EE

Tools

AMBA protocols (AHB/APB/AXI)

PCIe/UCIe interconnect

Job description

Amazon is seeking experienced Design Verification Engineers for the MLA team to design and optimize custom silicon for cloud AI workloads. You will verify SOC designs, integrate IPs, and develop comprehensive test plans and testbenches for Inferentia/Trainium chips in AWS data centers.

You will work with multiple verification platforms, use SystemVerilog/UVM, and mentor junior engineers while contributing to silicon yield and performance improvements on a global scale.