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Annapurna Labs (U.S.) Inc. in Austin, TX is seeking a senior ASIC Design Engineer to lead a team responsible for SOC integration of our ML accelerator chips. You will drive decisions across RTL, timing, DFT, and physical design to ensure timely milestones and high-quality silicon.
You will mentor engineers, establish top-level integration best practices, and collaborate with architecture, verification, and physical design teams to deliver cutting-edge hardware for AWS customers.
Annapurna Labs (U.S.) Inc. in Austin, TX is seeking a senior ASIC Design Engineer to lead a team responsible for SOC integration of our ML accelerator chips. You will drive decisions across RTL, timing, DFT, and physical design to ensure timely milestones and high-quality silicon.
You will mentor engineers, establish top-level integration best practices, and collaborate with architecture, verification, and physical design teams to deliver cutting-edge hardware for AWS customers.