Senior Microarchitecture Researcher

Entangled Future; Bothell (WA); On-site; USD 150,000 - 230,000; Full time

Job summary

IonQ in Bothell, WA invites a Senior Microarchitecture Researcher to join the Compute - Architecture team. You will design fault-tolerant chip architectures for ion-trap quantum processors and help translate theory into physical layouts and scalable silicon.

Collaborate with AMO physicists, QEC researchers, trap designers and other experts; publish results and contribute to a library of simulation tools used to evaluate performance under realistic noise.

Qualifications

• Four years of research experience in either quantum computing or chip architecture.
• Degree in quantum computing, physics, engineering, chemistry or related field.
• Expertise in AMO theory, QEC theory, QCVV theory or classical VLSI theory.

Responsibilities

• Contribute to the physical implementation of quantum error correction protocols on ion trap processors.
• Contribute to a library of simulation tools that analyse logical performance under realistic physical noise models.
• Collaborate with trap designers, AMO physicists, QEC researchers and a broad spectrum of other research backgrounds.
• Contribute to research papers and other technical writing.

Skills

Quantum simulation

Classical chip architecture

Quantum error correction

Communication across levels

Education

Degree in quantum computing/physics/engineering/chemistry or related field

Job description

Senior Microarchitecture Researcher at IonQ, Bothell, Washington, United States. A senior-level full time position in the Compute - Architecture team, listed under hardware engineering.

Role

We are looking for a Microarchitecture (uArch) Researcher. As a uArch researcher, you will be part of a cross-functional team whose mission is to lead IonQ on its journey to build the world's best quantum computers to solve the world's most complex problems. In this role, you will contribute to the physical implementation, design and layout of fault-tolerant architectures in ion trap quantum processors. You will work on implementing, tailoring, simulating and designing large-scale chip architectures that support fault-tolerant quantum computation. Your work will directly contribute to the physical and logical architecture of the quantum chips of the future.

Responsibilities

You will take quantum error correction protocols from theory to a physical layout on ion trap processors, and build the simulation tools that tell us how those layouts perform under realistic noise. The work is deeply collaborative. You will work alongside trap designers, AMO physicists, QEC researchers and colleagues from a broad range of research backgrounds, and share your results through papers and other technical writing.

Requirements

To succeed, you will need four years of research experience in either quantum computing or chip architecture, and a degree in quantum computing, physics, engineering, chemistry or a related field. You will bring strong expertise in one or more of AMO theory, QEC theory, QCVV theory or classical VLSI theory, and be comfortable applying it to the architecture of real quantum hardware.

You’d be a great fit with

• Strong expertise with quantum simulation techniques, including at the physical, gate, circuit and QEC level.
• Experience with classical chip architecture and an interest in quantum chip architecture.
• Experience with quantum error correction, logical operations and decoders.
• The ability to communicate at every level, from the research community to the business to PhD level.

Responsibilities

• Contribute to the physical implementation of quantum error correction protocols on ion trap processors.
• Contribute to a library of simulation tools that analyse logical performance under realistic physical noise models.
• Collaborate with trap designers, AMO physicists, QEC researchers and a broad spectrum of other research backgrounds.
• Contribute to research papers and other technical writing.