Senior Memory Systems Engineer: HBM/LPDDR Bringup & Validation

NVIDIA Corporation; Santa Clara (CA); Hybrid; USD 196,000 - 311,000; Full time

Benefits offered by this job

Equity

Comprehensive benefits

Hybrid work options

Job summary

NVIDIA's Silicon Co-Design Group is seeking a Senior Memory Systems Engineer to own HBM and LPDDR integration in next-generation SoCs. You will drive full-stack memory closure across silicon, package, board, and firmware, and lead post-silicon margining, eye and VF shmoo work.

The role requires 12+ years in high-speed memory systems, deep SI/PI expertise, and hands-on silicon bringup experience. You will collaborate across design, validation, firmware, and product teams in a fast-paced,

Qualifications

• BS or MS in EE/CE — or equivalent experience.
• 12+ years in HBM, LPDDR, or high-speed memory systems with hands-on depth in silicon bringup, characterization, and debug at scale.
• PHY controller development experience is a significant plus and will set you apart.
• Deep command of SI/PI, timing, margining, and memory training behavior — and the multi-functional fluency to work across design, package, firmware, validation, and product teams without losing the thread.
• HBM PHY and controller architecture familiarity is useful context, but what this role actually demands is rarer: the system-level instinct to see where memory behavior is about to become a product problem — and the inventiveness to resolve it before it does.

Responsibilities

• HBM & LPDDR system integration and bringup for next-generation SoCs, from first silicon to production-ready at scale.
• Own memory performance, power management, thermal, and reliability closure across silicon, package, board, and firmware.
• Lead post-silicon margining, VF shmoo, eye, and correlation work across voltage, temperature, and frequency.
• Debug and resolve memory training, calibration, SI/PI, and system-level stability issues.
• Define validation, characterization, and issue-tracking plans across chip programs.

Skills

HBM/LPDDR memory systems

Silicon bringup & debug

SI/PI timing & margining

Memory training behavior

PHY controller knowledge

Education

BS or MS in EE/CE

Job description

NVIDIA's Silicon Co-Design Group is seeking a Senior Memory Systems Engineer to own HBM and LPDDR integration in next-generation SoCs. You will drive full-stack memory closure across silicon, package, board, and firmware, and lead post-silicon margining, eye and VF shmoo work.

The role requires 12+ years in high-speed memory systems, deep SI/PI expertise, and hands-on silicon bringup experience. You will collaborate across design, validation, firmware, and product teams in a fast-paced,