Senior Principal DDR4/DDR5 Memory Validation Engineer

Rambus.com; San Jose (CA); Hybrid; USD 180,000 - 240,000; Full time

Benefits offered by this job

Equity

Employee benefits

Job summary

Rambus seeking an experienced applications engineer with DRAM and failure analysis expertise to support international customers of Rambus DDR4 and DDR5 memory interface chips. Analyze and debug complex issues in server memory, BIOS operation, and memory interface interactions.

The role involves occasional international travel, a hybrid work arrangement with onsite and remote work, and collaboration with Marketing and Engineering teams to deliver effective solutions.

Qualifications

• BS degree or higher in Electrical Engineering or related field.
• 12+ years of experience in hardware design, validation, and/or applications engineering.
• Excellent verbal and written communications in English and Korean.

Responsibilities

• Analyze and debug complex technical issues involving server memory with Rambus DDR4/DDR5 interface chips.
• Analyze and debug DRAM-related failures and collect signal integrity data.
• Travel to customer sites including international travel as needed.
• Prepare datasheets, user guides and application notes and present updates to customers.

Education

Bachelor's degree in Electrical Engineering

Tools

High speed oscilloscopes

ATE tester operation

server platform debug tools

Job description

Rambus seeking an experienced applications engineer with DRAM and failure analysis expertise to support international customers of Rambus DDR4 and DDR5 memory interface chips. Analyze and debug complex issues in server memory, BIOS operation, and memory interface interactions.

The role involves occasional international travel, a hybrid work arrangement with onsite and remote work, and collaboration with Marketing and Engineering teams to deliver effective solutions.