Memory Design Engineer

Mirafra Technologies; San Jose (CA); On-site; USD 140,000 - 200,000; Full time

Job summary

Mirafra Technologies in California seeks a memory design engineer to drive memory compiler development and transistor-level blocks. You will analyze architectures, simulate with transistor-level tools, and contribute to post-layout verification.

Responsibilities include floorplanning for physical macros, timing and power characterization, automation scripting, and documenting designs with timing diagrams. You will ensure silicon results align with simulations and participate in debugging and

Qualifications

• Memory compilers and custom macros design (SRAM, ROM, multi-ports).
• Transistor-level circuit behaviour and device physics.
• Signal integrity, EM/IR, and reliability analysis.
• Memory behavioural and physical models understanding.
• DFT schemes and chip-level integration.
• Silicon testing and debug familiarity.
• Automations scripts and simulator proficiency.
• Strong communication and leadership.
• Self-driven with multitasking ability.

Responsibilities

• Analyze different memory architectures and highlight the tradeoffs
• Design and build memory or circuit blocks at the gate or transistor level
• Simulate and analyse the circuit design using transistor level simulators
• Extract the layout and perform post-layout simulations and verification
• Floorplan physical implementation and leafcell layout integration to build the physical macro
• Integrate characterization flow to extract timing and power information
• Develop scripts to automate characterization flow, simulations, and verification
• Specify and verify various behavioural and physical memory models
• Document the design specifications, behavioural description, and timing diagrams
• Specify silicon test plan and correlate silicon to simulation data

Skills

Memory compiler development

Transistor-level circuits

Signal integrity / EM/IR

Memory models (behavioral/physical)

DFT schemes

Silicon testing

Automation scripting

Communication skills

Self-driven

Multitasking

Tools

Circuit simulators

Automation scripts

Job description

• Analyse different memory architectures and highlight the tradeoffs
• Design and build memory or circuit blocks at the gate or transistor level
• Simulate and analyse the circuit design using transistor level simulators
• Extract the layout and perform post-layout simulations and verification
• Floorplan physical implementation and leafcell layout integration to build the physical macro
• Integrate characterization flow to extract timing and power information
• Develop scripts to automate characterization flow, simulations, and verification
• Specify and verify various behavioural and physical memory models
• Document the design specifications, behavioural description, and timing diagrams
• Specify silicon test plan and correlate silicon to simulation data

Skillset Required

• Strong Expertise in development of memory compilers and custom macros of all types; SRAMs, Register-files, Multi-ports, ROM, etc…
• Deep understanding of transistor level circuit behaviour and device physics
• Deep understanding of signal integrity analysis, EM/IR analysis, and reliability analysis
• Good understanding of memory behavioural and physical models
• Good understanding of DFT schemes and chip level integration
• Familiar with test setups, silicon testing and debug
• Proficient in running simulators, writing automation scripts, and are tools savvy
• Good communication, interpersonal, and leadership skills
• Motivated, self-driven and good at multi-tasking