Senior Logic Design Engineer - High-Perf Memory Controllers

Rambus.com; Hillsboro, Northern (OR, KY); Hybrid; USD 127,000 - 237,000; Full time

Benefits offered by this job

Gym membership

Equity & stock plans

401(k) match

Employee stock purchase plan

Medical & dental benefits

Time-off program

Job summary

Rambus is seeking a Principal Logic Design Engineer in Hillsboro, Oregon to lead micro-architecture and RTL for high-performance memory controllers. You will partner with verification, physical design, and field teams to ensure robust, scalable designs for data centers and AI workloads.

The role emphasizes independent work, strong communication, and the ability to learn quickly in a fast-moving semiconductor environment. Hybrid onsite/remote work is offered.

Qualifications

• 10+ years of logic design experience (ASIC/FPGA) with a BSEE, or
• 8+ years with an MSEE degree
• Strong RTL design and verification background
• Experience with memory controller/ASIC projects

Responsibilities

• Own micro-architecture and RTL for schedulers, pipelines and interfaces
• Analyze PPA, drive design decisions with data
• Collaborate with verification to improve coverage
• Coordinate with physical design to resolve timing/power
• Support FAE and AE teams on customer engagements
• Provide RTL fixes and debug regression failures

Skills

SystemVerilog RTL

Verilog RTL

Python/Perl/TCL scripting

Independence/initiative

Communication & PM

Education

BSEE

MSEE

Tools

Questa/Incisive/VCS simulators

Job description

Rambus is seeking a Principal Logic Design Engineer in Hillsboro, Oregon to lead micro-architecture and RTL for high-performance memory controllers. You will partner with verification, physical design, and field teams to ensure robust, scalable designs for data centers and AI workloads.

The role emphasizes independent work, strong communication, and the ability to learn quickly in a fast-moving semiconductor environment. Hybrid onsite/remote work is offered.