Principal Design Verification Engineer - Hybrid DDR Focus

Rambus.com; Hillsboro (OR); Hybrid; USD 127,000 - 237,000; Full time

Benefits offered by this job

Gym membership

Health benefits

401(k) matching

Employee stock purchase plan

Job summary

Rambus seeks a Senior/Principal Design Verification Engineer to join the Memory Controller IP team in Hillsboro, Oregon. You will contribute to pre-silicon RTL verification for DDR, HBM, and GDDR DRAM controller technologies and report to the local onsite manager.

Hybrid work is offered; three days on-site and two days remote is encouraged for office-based roles. The role emphasizes testbench development, coverage planning, and regression debugging across RTL designs.

Qualifications

• BS degree or higher in EE/CS with 10+ years HDL verification experience.
• Proficient in SystemVerilog testbenches and Verilog/SystemVerilog RTL.
• Experience with DDR DRAM technologies preferred.
• Python and TCL scripting experience preferred.

Responsibilities

• Testbench and test sequence development for verification of new controller technologies and features.
• Functional coverage planning, coverage item coding, and test suite augmentation to achieve Functional Coverage.
• Regression test development, monitoring, debug/triage, and correction to test environment, sequences, debug of controller RTL design.
• Development and support of Verification environment scripting and capabilities.

Skills

SystemVerilog

Verilog

HDL verification

Python

DDR DRAM knowledge

TCL scripting

Education

Bachelor's degree in EE/CS

Job description

Rambus seeks a Senior/Principal Design Verification Engineer to join the Memory Controller IP team in Hillsboro, Oregon. You will contribute to pre-silicon RTL verification for DDR, HBM, and GDDR DRAM controller technologies and report to the local onsite manager.

Hybrid work is offered; three days on-site and two days remote is encouraged for office-based roles. The role emphasizes testbench development, coverage planning, and regression debugging across RTL designs.