Senior JTAG & DFT Architect — Equity & Hybrid

NVIDIA Corporation; Santa Clara (CA); Hybrid; USD 168,000 - 311,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA Corporation, a leader in GPU and AI hardware, seeks a Senior JTAG Methodology Engineer in Santa Clara, CA. You will architect and develop test methodologies to make next-gen silicon testable, debuggable, and secure from bring-up.

You will partner with cross-functional teams to optimize trade-offs between cost and quality. The role emphasizes JTAG, DFT, RTL design, and post-silicon validation, with mentoring responsibilities and collaboration across timing, software, and production groups.

Qualifications

• BS/MS degree in Electrical or Computer Engineering (or equivalent) with DFT/JTAG experience.
• 5+ years hands-on experience in SoC architecture, RTL design and verification.
• Strong analytical skills with experience verifying test patterns and logic on complex designs.
• Experience in JTAG, silicon debug, and bring-up on ATE with pattern formats and failure processing.

Responsibilities

• Own and drive JTAG/DFT methodologies for next-gen products.
• Collaborate with timing, physical design, software, bring-up, and production teams to balance cost and quality.
• Architect, develop and deploy DFT methodologies across RTL design, verification and post-silicon validation.
• Mentor junior engineers on test designs and trade-offs.

Skills

JTAG methodology

Silicon debug

Mentoring engineers

Cross-functional collab

Scripting (Perl/Python/Tcl)

Education

BS/MS Electrical or Computer Engineering

Tools

DFT tools

RTL design tools

Job description

NVIDIA Corporation, a leader in GPU and AI hardware, seeks a Senior JTAG Methodology Engineer in Santa Clara, CA. You will architect and develop test methodologies to make next-gen silicon testable, debuggable, and secure from bring-up.

You will partner with cross-functional teams to optimize trade-offs between cost and quality. The role emphasizes JTAG, DFT, RTL design, and post-silicon validation, with mentoring responsibilities and collaboration across timing, software, and production groups.