Senior Interconnect Fabric Verification Engineer

NUVACORE; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

NUVACORE is building a high-performance, low-power CPU for next-generation compute workloads. We are seeking Verification Engineers at multiple levels—from Senior Engineer to Principal—to help prove the correctness of the NUVACORE interconnect fabric.

As part of the design verification (DV) team, you will help verify the coherent and non-coherent interconnect — building the test plans, environments, and checkers that find deep bugs in transport, ordering, and coherence long before silicon,

Qualifications

• Degree in Electrical/Computer Engineering, Computer Science, or equivalent practical experience.
• 15+ years (Principal) or 4+ years (Senior Engineer) of design-verification experience on CPU or complex digital design.
• Strong knowledge of interconnect/fabric architecture and digital logic, including coherent/non-coherent protocols.
• Hands-on functional verification: test plans, testbenches, protocol checkers, transactors, coverage.
• Proficiency in C/C++ and/or SystemVerilog, plus a scripting language (Python preferred).
• Experience writing and debugging tests for complex digital designs.

Responsibilities

• Plan and drive verification scope, strategy, and test plans for the interconnect fabric.
• Build and maintain verification environments with stimulus generators, checkers, and coverage.
• Generate directed and random traffic to expose corner cases, including ordering and QoS.
• Verify RTL vs performance models, identifying bandwidth and latency issues.
• Define coverage space, write functional coverage monitors, and ensure closure.
• Collaborate with architecture and RTL teams to root-cause failures and support bring-up.

Skills

Test planning

Coverage metrics

Debugging

Verilog/SystemVerilog

C/C++

Python scripting

Education

Bachelor's degree in Electrical/Computer Engineering or Computer Science

Tools

SystemVerilog

C/C++

Python

Job description

NUVACORE is building a high-performance, low-power CPU for next-generation compute workloads. We are seeking Verification Engineers at multiple levels—from Senior Engineer to Principal—to help prove the correctness of the NUVACORE interconnect fabric.

As part of the design verification (DV) team, you will help verify the coherent and non-coherent interconnect — building the test plans, environments, and checkers that find deep bugs in transport, ordering, and coherence long before silicon,