CPU Fabric and Interconnect Verification Engineer

NUVACORE; Santa Clara (CA); Vor Ort; USD 180.000 - 260.000; Vollzeit

Zusammenfassung

Nuvacore is building a ground-up high performance, low-power CPU for next‑generation compute workloads. We are seeking Verification Engineers at multiple levels — Senior Engineer to Principal — to help prove the correctness of the Nuvacore interconnect fabric.

You will design verification environments, write test plans, and develop checkers that uncover deep bugs long before silicon. Join a DV team that collaborates with architecture and RTL to ensure robust ordering, QoS, and deadlock avoidance

Qualifikationen

• Degree in Electrical/Computer Engineering, Computer Science, or equivalent practical experience.
• 15+ years (Principal) or 4+ years (Senior Engineer) of design‑verification experience.
• Strong knowledge of interconnect/fabric architecture and digital logic — coherent and non‑coherent protocols (e.g. AMBA, CHI, TileLink) and on‑chip transport.
• Hands‑on functional verification: test plans, testbenches, protocol checkers, transactors, and coverage.
• Proficiency in C/C++ and/or SystemVerilog, plus a scripting language (Python; Perl a plus).
• Experience writing and debugging tests for complex digital designs.

Aufgaben

• Plan & Strategy: Drive the verification scope, strategy, and test plans for the interconnect fabric — coherent and non‑coherent, including crossbars, routing, and bus interfaces.
• Environment Setup: Build, maintain, and scale robust verification environments — stimulus generators, protocol checkers, transactors, and coverage — that exercise coherent and non‑coherent transactions end to end.
• Test & Debug: Generate directed and random traffic to expose corner cases such as ordering, arbitration, QoS, and deadlock/livelock avoidance.
• Performance Verification: Partner with architects to correlate RTL against performance models, hunting bandwidth, latency, and QoS issues.
• Coverage Closure: Define the coverage space, write functional coverage monitors, and analyze metrics to prove the test plan is complete.
• Cross-functional Collaboration: Partner with architecture and RTL teams to root-cause failures, drive design fixes, and support emulation, FPGA, and silicon bring-up.

Kenntnisse

Design verification

Interconnect architecture

Digital logic

SystemVerilog

C/C++

Python

Testbenches

Test plans

Protocol checkers

Transactors

Coverage

Ausbildung

Electrical/Computer Engineering

Computer Science

Jobbeschreibung

Nuvacore is building a ground-up high performance, low-power CPU for next-generation compute workloads. We are seeking Verification Engineers at multiple levels — from Senior Engineer to Principal level — to help prove the correctness of the Nuvacore interconnect fabric. As part of the design verification (DV) team, you will help verify the coherent and non-coherent interconnect — building the test plans, environments, and checkers that find deep bugs in transport, ordering, and coherence long before silicon, working shoulder-to-shoulder with architecture and RTL design.

THE ROLE

• Plan & Strategy: Drive the verification scope, strategy, and test plans for the interconnect fabric — coherent and non-coherent, including crossbars, routing, and bus interfaces.
• Environment Setup: Build, maintain, and scale robust verification environments — stimulus generators, protocol checkers, transactors, and coverage — that exercise coherent and non-coherent transactions end to end.
• Test & Debug: Generate directed and random traffic to expose corner cases such as ordering, arbitration, QoS, and deadlock/livelock avoidance.
• Performance Verification: Partner with architects to correlate RTL against performance models, hunting bandwidth, latency, and QoS issues.
• Coverage Closure: Define the coverage space, write functional coverage monitors, and analyze metrics to prove the test plan is complete.
• Cross-functional Collaboration: Partner with architecture and RTL teams to root-cause failures, drive design fixes, and support emulation, FPGA, and silicon bring-up.

Requirements — Must Have

• Degree in Electrical/Computer Engineering, Computer Science, or equivalent practical experience.
• 15+ years (Principal) or 4+ years (Senior Engineer) of design-verification experience, ideally on a CPU or complex digital design.
• Strong knowledge of interconnect/fabric architecture and digital logic — coherent and non-coherent protocols (e.g. AMBA, CHI, TileLink) and on-chip transport.
• Hands-on functional verification: test plans, testbenches, protocol checkers, transactors, and coverage.
• Proficiency in C/C++ and/or SystemVerilog, plus a scripting language (Python; Perl a plus).
• Experience writing and debugging tests for complex digital designs.

Requirements — Nice To Have

• Interconnect, network-on-chip (NoC), or fabric verification.
• Coherent and non-coherent bus-protocol verification.
• Protocol checkers and formal verification (deadlock/livelock, protocol compliance).
• Constrained-random verification and coverage-driven closure.
• Performance and QoS verification of interconnect.
• Emulation/FPGA and silicon bring-up and debug (waveforms, trace).

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.