Senior CPU Verification Engineer — End-to-End Validation

NUVACORE; Santa Clara (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

NUVACORE is building a high‑performance, low‑power CPU and seeks Verification Engineers at Senior and Principal levels to strengthen the DV team in Santa Clara, CA. You will design test plans, environments, checkers, and coverage to exercise the pipeline end‑to‑end long before silicon.

You will collaborate with architecture and RTL to debug failures, close coverage, and drive sign‑offs on complex CPU features.

Qualifications

• Degree in Electrical/Computer Engineering, Computer Science, or equivalent practical experience.
• 4+ years (Senior) or 15+ years (Principal) of design‑verification experience, ideally on CPU or complex digital design.
• Strong knowledge of CPU micro-architecture: pipelines, out‑of‑order execution, and branch prediction.
• Hands‑on verification: test plans, testbenches, checkers and coverage writing.

Responsibilities

• Plan & Strategy: drive verification scope, strategy, and test plans for the CPU design.
• Environment Setup: build and maintain robust verification environments and coverage.
• Test & Debug: generate directed and random tests in assembly, C, or RIS.
• Performance Verification: correlate RTL against models; analyze throughput and predictions.
• Coverage Closure: define coverage space and analyze metrics to prove test completeness.
• Cross‑functional Collaboration: partner with architecture and RTL for fixes and bring‑up.

Skills

CPU verification

SystemVerilog

C/C++

Python scripting

Testbenches

Coverage

Education

Bachelors in Electrical/Computer Engineering or Computer Science

Tools

SystemVerilog

C/C++

Python

Job description

NUVACORE is building a high‑performance, low‑power CPU and seeks Verification Engineers at Senior and Principal levels to strengthen the DV team in Santa Clara, CA. You will design test plans, environments, checkers, and coverage to exercise the pipeline end‑to‑end long before silicon.

You will collaborate with architecture and RTL to debug failures, close coverage, and drive sign‑offs on complex CPU features.