Interconnect Fabric Verification Architect

NUVACORE; Santa Clara (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Nuvacore is building a ground-up high performance, low-power CPU for next‑generation compute workloads. We are seeking Verification Engineers at multiple levels — Senior Engineer to Principal — to help prove the correctness of the Nuvacore interconnect fabric.

You will design verification environments, write test plans, and develop checkers that uncover deep bugs long before silicon. Join a DV team that collaborates with architecture and RTL to ensure robust ordering, QoS, and deadlock avoidance

Qualifications

• Degree in Electrical/Computer Engineering, Computer Science, or equivalent practical experience.
• 15+ years (Principal) or 4+ years (Senior Engineer) of design‑verification experience.
• Strong knowledge of interconnect/fabric architecture and digital logic — coherent and non‑coherent protocols (e.g. AMBA, CHI, TileLink) and on‑chip transport.
• Hands‑on functional verification: test plans, testbenches, protocol checkers, transactors, and coverage.
• Proficiency in C/C++ and/or SystemVerilog, plus a scripting language (Python; Perl a plus).
• Experience writing and debugging tests for complex digital designs.

Responsibilities

• Plan & Strategy: Drive the verification scope, strategy, and test plans for the interconnect fabric — coherent and non‑coherent, including crossbars, routing, and bus interfaces.
• Environment Setup: Build, maintain, and scale robust verification environments — stimulus generators, protocol checkers, transactors, and coverage — that exercise coherent and non‑coherent transactions end to end.
• Test & Debug: Generate directed and random traffic to expose corner cases such as ordering, arbitration, QoS, and deadlock/livelock avoidance.
• Performance Verification: Partner with architects to correlate RTL against performance models, hunting bandwidth, latency, and QoS issues.
• Coverage Closure: Define the coverage space, write functional coverage monitors, and analyze metrics to prove the test plan is complete.
• Cross-functional Collaboration: Partner with architecture and RTL teams to root-cause failures, drive design fixes, and support emulation, FPGA, and silicon bring-up.

Skills

Design verification

Interconnect architecture

Digital logic

SystemVerilog

C/C++

Python

Testbenches

Test plans

Protocol checkers

Transactors

Coverage

Education

Electrical/Computer Engineering

Computer Science

Job description

Nuvacore is building a ground-up high performance, low-power CPU for next‑generation compute workloads. We are seeking Verification Engineers at multiple levels — Senior Engineer to Principal — to help prove the correctness of the Nuvacore interconnect fabric.

You will design verification environments, write test plans, and develop checkers that uncover deep bugs long before silicon. Join a DV team that collaborates with architecture and RTL to ensure robust ordering, QoS, and deadlock avoidance