CPU Architecture Verification Engineer – Next‑Gen Compute

NUVACORE, Inc.; Austin (TX); Hybrid; USD 140,000 - 210,000; Full time

Job summary

Nuvacore, Inc. is hiring Verification Engineers at multiple levels to ensure the Nuvacore CPU is architecturally correct. You will join the design verification team to build stimuli, checkers, and flows, and drive verification strategy across the project.

Responsibilities include planning scope, setting up robust environments, and performing test and debug with assembly and RIS. Collaboration with architects and RTL is essential for root-causes and coverage closure.

Qualifications

• Degree in Electrical/Computer Engineering, Computer Science, or equivalent practical experience.
• 4+ years (Senior Engineer) or 15+ years (Principal) of design-verification experience on CPUs or complex digital designs.
• Strong knowledge of CPU architecture, ISA (x86/ARM/RISC-V), and architectural state.
• Hands-on verification: test plans, testbenches, checkers, and coverage.

Responsibilities

• Plan verification scope, strategy, and test plans for architectural correctness.
• Build robust verification environments and co-simulation against a golden reference model.
• Create assembly and RIS stimulus; exercise exceptions, interrupts, and privilege transitions.
• Define coverage space, monitors, and analyze metrics for closure.
• Collaborate with architects, RTL, emulation, FPGA, and silicon bring-up.

Skills

CPU architecture knowledge

Verification fundamentals

Assembly verification

SystemVerilog/C/C++/Rust

RIS stimulus generation

Education

Degree in Electrical/Computer Engineering, Computer Science, or equivalent

Tools

SystemVerilog

Python scripting

C/C++

Job description

Nuvacore, Inc. is hiring Verification Engineers at multiple levels to ensure the Nuvacore CPU is architecturally correct. You will join the design verification team to build stimuli, checkers, and flows, and drive verification strategy across the project.

Responsibilities include planning scope, setting up robust environments, and performing test and debug with assembly and RIS. Collaboration with architects and RTL is essential for root-causes and coverage closure.