Senior IC Design Engineer - Low-Power & PnR Specialist

Broadcom; Irvine (CA); On-site; USD 122,000 - 195,000; Full time

Benefits offered by this job

Discretionary annual bonus

Equity grant

401(k) with company match

ESPP

Paid holidays and time off

Job summary

Broadcom is seeking an experienced physical design engineer to join a team responsible for ASIC flow from netlist to GDSII. You will perform floorplanning, partitioning, and block pin assignments, and drive PnR, timing closure, and physical verification. Knowledge of IR/EM analysis and low-power IC design is valuable.

Proficiency in tcl/perl/python and Calibre is preferred. The role requires a Bachelor’s degree with 8+ years or a Master’s with 6+ years; on-site collaboration in Irvine/San Jose

Qualifications

• Bachelor’s degree and 8+ years of related experience or Master’s degree with 6+ years of experience.
• Experience in physical design flow from netlist to GDSII.
• Familiar with scripting to automate the physical design flow.

Responsibilities

• Work as part of a physical design team implementing chips from netlist to GDSII.
• Responsible for floorplanning, design partitioning, and block pin assignment.
• Perform block PnR, timing closure, and physical verification.
• Perform block IR/EM analysis. Experience with chip level IR/EM analysis is a big plus.
• Familiar with scripting languages such as tcl, perl and python. Write scripts to automate the physical design flow and increase efficiency.
• Expertise in low-power IC design is desirable.
• Good knowledge of physical verification using Mentor’s Calibre tool.

Skills

Scripting abilities

Low-power IC design

IR/EM analysis

Education

Bachelor's degree

Master's degree

Tools

tcl

perl

python

Mentor Calibre

Job description

Broadcom is seeking an experienced physical design engineer to join a team responsible for ASIC flow from netlist to GDSII. You will perform floorplanning, partitioning, and block pin assignments, and drive PnR, timing closure, and physical verification. Knowledge of IR/EM analysis and low-power IC design is valuable.

Proficiency in tcl/perl/python and Calibre is preferred. The role requires a Bachelor’s degree with 8+ years or a Master’s with 6+ years; on-site collaboration in Irvine/San Jose