PCB Layout Engineer

HCLTech; Menlo Park (CA); On-site; USD 88,000 - 148,000; Full time

Benefits offered by this job

Medical, dental, vision

401(k) retirement plan

10 days paid time off

10 paid holidays

Job summary

HCLTech is seeking an experienced PCB Layout Engineer in Menlo Park, CA, to lead complex server and data center board layouts using Cadence Allegro. You will own end-to-end layout activities for high-density designs featuring DDR5, PCIe Gen5/Gen6, and high-speed interfaces.

Collaborate with electrical and mechanical teams on constraints, routing, power integrity, and manufacturability while delivering robust designs and documentation for prototype and production builds.

Qualifications

• 8+ years of PCB layout and CAD design experience.
• Expert-level proficiency with Cadence Allegro.
• Hands-on expertise with HDI, blind/buried vias, and microvia technologies.
• Proven experience designing boards based on SoCs, Microprocessors, FPGAs, or Intel platforms.

Responsibilities

• Own end-to-end PCB layout activities for complex, high-density server and datacenter hardware designs.
• Perform high-speed PCB layout for interfaces including DDR4/DDR5, LPDDR5, PCIe Gen5/Gen6, HBM, USB, and other high-speed buses.
• Develop and enforce layout constraints related to controlled impedance, length matching, signal integrity, power integrity, and crosstalk mitigation.
• Collaborate closely with electrical engineers to review schematics, optimize component placement, power distribution networks, and routing strategies.
• Partner with mechanical teams to resolve board outline, stack-up, thermal, connector placement, and enclosure constraints.
• Execute HDI PCB designs utilizing blind, buried, and microvia technologies.
• Drive DFM, DFA, and DFT reviews with PCB fabricators and contract manufacturers to ensure manufacturability, reliability, and yield.
• Maintain PCB libraries, stack-up definitions, design standards, and layout best practices.
• Support prototype and production builds through layout documentation, net tracing, design analysis, and engineering change implementation.

Skills

HDI vias

SoCs/FPGA experience

Intel platforms

Tools

Cadence Allegro

Job description

HCLTech is looking for a highly talented and self-motivated PCB Layout Engineer to join it in advancing the technological world through innovation and creativity.

Job Title: PCB Layout Engineer

Job ID: 111699

Position Type: Full Time

We are seeking an experienced PCB Layout Engineer with deep expertise in Cadence Allegro PCB Design to support the development of next-generation server, datacenter, and high-performance computing platforms. The ideal candidate will have extensive experience delivering complex, high-density, high-speed PCB layouts involving DDR5, PCIe Gen5/Gen6, power delivery, FPGA, SoC, and mixed-signal designs.

Key Responsibilities

• Own end-to-end PCB layout activities for complex, high-density server and datacenter hardware designs.
• Perform high-speed PCB layout for interfaces including DDR4/DDR5, LPDDR5, PCIe Gen5/Gen6, HBM, USB, and other high-speed buses.
• Develop and enforce layout constraints related to controlled impedance, length matching, signal integrity, power integrity, and crosstalk mitigation.
• Collaborate closely with electrical engineers to review schematics, optimize component placement, power distribution networks, and routing strategies.
• Partner with mechanical teams to resolve board outline, stack-up, thermal, connector placement, and enclosure constraints.
• Execute HDI PCB designs utilizing blind, buried, and microvia technologies.
• Drive DFM, DFA, and DFT reviews with PCB fabricators and contract manufacturers to ensure manufacturability, reliability, and yield.
• Maintain PCB libraries, stack-up definitions, design standards, and layout best practices.
• Support prototype and production builds through layout documentation, net tracing, design analysis, and engineering change implementation.

Required Qualifications

• 8+ years of PCB layout and CAD design experience.
• Expert-level proficiency with Cadence Allegro.
• Hands‑on expertise with HDI, blind/buried vias, and microvia technologies.
• Proven experience designing boards based on SoCs, Microprocessors, FPGAs, or Intel platforms.

Pay and Benefits

Pay Range Minimum: $78000/Year

Pay Range Maximum: $148000/Year

HCLTech is an equal opportunity employer, committed to providing equal employment opportunities to all applicants and employees regardless of race, religion, sex, color, age, national origin, pregnancy, sexual orientation, physical disability or genetic information, military or veteran status, or any other protected classification, in accordance with federal, state, and/or local law. Should any applicant have concerns about discrimination in the hiring process, they should provide a detailed report of those concerns to [e-mail] for investigation.

A candidate’s pay within the range will depend on their skills, experience, education, and other factors permitted by law. This role may also be eligible for performance-based bonuses subject to company policies. In addition, this role is eligible for the following benefits subject to company policies: medical, dental, vision, pharmacy, life, accidental death & dismemberment, and disability insurance; employee assistance program; 401(k) retirement plan; 10 days of paid time off per year (some positions are eligible for need-based leave with no designated number of leave days per year); and 10 paid holidays per year

How You’ll Grow

At HCLTech, we offer continuous opportunities for you to find your spark and grow with us. We want you to be happy and satisfied with your role and to really learn what type of work sparks your brilliance the best. Throughout your time with us, we offer transparent communication with senior-level employees, learning and career development programs at every level, and opportunities to experiment in different roles or even pivot industries. We believe that you should be in control of your career with unlimited opportunities to find the role that fits you best.