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Hewlett Packard Enterprise in Sunnyvale, CA is seeking a Senior PCB Layout Engineer to design high-performance, multi-layer PCBs using Cadence Allegro. You will lead critical hardware projects, ensure signal integrity, and drive manufacturing readiness while mentoring junior designers.
Role focuses on constraint-driven layout, impedance-controlled stackups, HDI techniques, and collaboration with SI/PI, mechanical and manufacturing teams to enable first-pass success for networking, servers and
Hewlett Packard Enterprise in Sunnyvale, CA is seeking a Senior PCB Layout Engineer to design high-performance, multi-layer PCBs using Cadence Allegro. You will lead critical hardware projects, ensure signal integrity, and drive manufacturing readiness while mentoring junior designers.
Role focuses on constraint-driven layout, impedance-controlled stackups, HDI techniques, and collaboration with SI/PI, mechanical and manufacturing teams to enable first-pass success for networking, servers and