Senior PCB Layout Engineer

Hewlett Packard Enterprise; Sunnyvale (CA); On-site; USD 106,000 - 214,000; Full time

Job summary

Hewlett Packard Enterprise in Sunnyvale, CA is seeking a Senior PCB Layout Engineer to design high-performance, multi-layer PCBs using Cadence Allegro. You will lead critical hardware projects, ensure signal integrity, and drive manufacturing readiness while mentoring junior designers.

Role focuses on constraint-driven layout, impedance-controlled stackups, HDI techniques, and collaboration with SI/PI, mechanical and manufacturing teams to enable first-pass success for networking, servers and

Qualifications

• 8–15+ years of PCB layout experience.
• Expert proficiency in Cadence Allegro.
• Strong knowledge of high-speed design techniques.
• Impedance control and stackup planning.
• HDI technologies and EMI/EMC fundamentals.
• Solid understanding of PCB fabrication and assembly processes.

Responsibilities

• Design complex boards (12–40+ layers) using Cadence Allegro.
• Perform optimized component placement for high-speed digital, power, thermal and EMI control.
• Route PCIe, DDR4/DDR5, USB-C and Ethernet interfaces with controlled impedance.
• Define and manage rules using Constraint Manager and develop stackups with fabrication feasibility.
• Mentor junior designers and lead layout planning and design reviews.

Skills

PCB layout experience

High-speed design

Impedance control

HDI technologies

EMI/EMC fundamentals

PCB fabrication knowledge

Tools

Cadence Allegro

Job description

This role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office.

Who We Are:

Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world.Our culture thrives onfinding new and better ways to accelerate what’s next.We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs.We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you.Open up opportunities with HPE.

Job Description:

Senior PCB Layout Engineer

A Senior PCB Layout Engineer is a technical expert responsible for designing complex, high-speed printed circuit boards using the Cadence Design Systems Allegro PCB Designer platform. This role focuses on advanced constraint-driven layout, signal integrity awareness, manufacturing readiness, and automation (often with SKILL), while leading critical hardware projects.

Role Summary

Design and deliver high-performance, multi-layer PCBs for complex electronic systems such as networking equipment, servers, telecom hardware, aerospace systems, or high-speed embedded platforms. The engineer works closely with hardware, SI/PI, mechanical, and manufacturing teams to ensure first-pass success and production readiness.

Key Responsibilities

Advanced PCB Layout

• Design complex boards (12–40+ layers) using Cadence Allegro PCB Designer
• Perform optimized component placement for:
  • High-speed digital
  • Power distribution
  • Thermal performance
  • EMI control
• Route critical interfaces:
  • DDR4/DDR5
  • PCIe Gen4/Gen5+
  • USB 3.x / Type-C
  • Ethernet (10G–112G SerDes)
• Implement:
  • Differential pair routing and tuning
  • Length and phase matching
  • Controlled impedance structures

Constraint & Stackup Management

• Define and manage rules using Constraint Manager
• Develop stackups with controlled impedance and fabrication feasibility
• Work with PCB vendors to validate materials, via structures, and HDI capability

Signal Integrity & Power Integrity Awareness

• Apply SI/PI best practices:
  • Return path continuity
  • Crosstalk reduction
  • Proper decoupling strategy
• Collaborate with SI/PI teams

HDI and Advanced Technologies

• Blind/buried vias and microvias
• BGA escape for high pin-count devices
• Backdrilling for high-speed signals
• High-current and low-noise power routing

Manufacturing & NPI Support

• Generate fabrication and assembly outputs:
  • ODB++, IPC-2581, Gerber
  • Drill files, drawings, stackup documentation
• Perform DFM/DFA reviews with vendors
• Support prototype builds and resolve manufacturing issues

Leadership

• Mentor junior and mid-level PCB designers
• Lead layout planning and design reviews
• Estimate schedules and manage multiple projects

Required Qualifications

• 8–15+ years of PCB layout experience
• Expert proficiency in Cadence Allegro
• Strong knowledge of:
  • High-speed design techniques
  • Impedance control and stackup planning
  • HDI technologies
  • EMI/EMC fundamentals
• Solid understanding of PCB fabrication and assembly processes

Preferred (High-End Systems)

• Networking, server, or telecom hardware experience
• Familiarity with:
  • 25G/56G/112G SerDes
  • Backplane design
  • Thermal/mechanical co-design
• Experience with SI/PI analysis tools

Typical Impact

• Enables first-pass board success (fewer respins)
• Supports higher data rates and system reliability
• Improves team efficiency through automation
• Serves as the technical authority for PCB layout

What We Can Offer You:

We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.

Personal & Professional Development

We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division.

Unconditional Inclusion

We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.

Let’s Stay Connected:

Follow @HPECareers on Instagram to see the latest on people, culture and tech at HPE.

#unitedstates

#networking

Job:

Job Level:

TCP_03

The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level.
— United States of America: Annual Salary USD 105,500 - 213,500 in California
The listed salary range reflects base salary. Variable incentives may also be offered.

HPE is an Equal Employment Opportunity/ Veterans/Disabled/LGBT employer. We do not discriminate on the basis of race, gender, or any other protected category, and all decisions we make are made on the basis of qualifications, merit, and business need. Our goal is to be one global team that is representative of our customers, in an inclusive environment where we can continue to innovate and grow together. Please click here: Equal Employment Opportunity .

Hewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities.

HPE will comply with all applicable laws related to employer use of arrest and conviction records, including laws requiring employers to consider for employment qualified applicants with criminal histories.

Hewlett Packard Enterprise is a global edge-to-cloud company focused on driving innovation and technology solutions for businesses across diverse industries.

IT Services and IT Consulting Professional Services

Post IPO Equity - Elliott Management Corp.$1.5B

Apr 2025

Post IPO Equity$1.3B

Sep 2024

Footprint

Where they work

Headquarters Houston, Texas

1701 E Mossy Oaks Rd Spring, Houston, Texas 77389, US

Apply For This Role

Location Sunnyvale, California, United States